component
AP7311-18WG-7
Public Made by Adomby adom
Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-25. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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ap7311-18wg-7: specified limits as data (metadata.characteristics, 22 rows from the datasheet)
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AP7311-18WG-7
Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25
AP7311-18WG-7 from Diodes Incorporated, in a SOT-25. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Voltage input pin (2V to 6V, 7V absolute max). Bypass to ground through at least 1uF capacitor. |
| 2 | GND | power_in | Ground reference pin. |
| 3 | EN | input | Enable input, active high. VIH = 1.4V min, VIL = 0.4V max. Referenced to VIN (max VIN + 0.3V). |
| 4 | NC | unconnected | No connection. This pin is unused on the fixed-output variant (AP7311-18WG-7 is a fixed 1.8V output part). |
| 5 | OUT | power_out | Regulated voltage output pin, fixed 1.8V, 150mA max. Bypass to ground through 1uF ceramic capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25 |
| Category | PMIC |
| Pins | 5 |
Ordering variants
AP7311-18WG-7AP7311-18WG-7AP7311-WG-7
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| ESD HBM Human Body Model ESD Protection | ESD HBM | 6 | kV | Human Body Model ESD Protection | 4 | ||
| ESD MM Machine Model ESD Protection | ESD MM | 400 | V | Machine Model ESD Protection | 4 | ||
| Input Voltage | VIN | 7 | V | 4 | |||
| Operating Junction Temperature Range | TOP | -40 | 125 | °C | 4 | ||
| Storage Temperature Range | TST | -65 | 150 | °C | 4 | ||
| Power Dissipation | PD | 640 | mW | SOT25; ratings apply to ambient temperature at 25°C (Note 3) | 4 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 4 | |||
| Input voltage | VIN | 2 | 6 | V | 4 | ||
| Output Current | IOUT | 0 | 150 | mA | Note 4: device maintains stable regulated output without load current | 4 | |
| Operating Ambient Temperature | TA | -40 | 85 | °C | 4 | ||
| Input Quiescent Current | IQ | 55 | 75 | μA | VEN = VIN, IOUT = 0mA | 5 | |
| Input Quiescent Current | IQ | 65 | 85 | μA | VEN = VIN, IOUT = 150mA | 5 | |
| Input Shutdown Current | ISHDN | 1 | μA | VEN = 0V, IOUT = 0mA | 5 | ||
| Input Leakage Current | ILEAK | 1 | μA | VEN = 0V, OUT grounded | 5 | ||
| Output Voltage Accuracy | VOUT | -2 | 2 | % | TA = -40°C to 85°C, IOUT = 30mA | 5 | |
| Line Regulation | ΔVOUT/ΔVIN/V | 0.01 | 0.2 | %/V | VIN = (VOUT +1V) to VIN-Max, VEN = VIN, IOUT = 1mA | 5 | |
| Load Regulation | ΔVOUT/VOUT | -0.6 | 0.6 | % | VIN = (VOUT +1V) to VIN-Max, IOUT from 1mA to 150mA | 5 | |
| Current Limit | ILIMIT | 200 | 300 | mA | VIN = (VOUT +1V) to VIN-Max, VOUT/ROUT = 0.5A | 5 | |
| EN Input Logic Low Voltage | VIL | 0.4 | V | VIN = VIN-Min to VIN-Max | 5 | ||
| EN Input Logic High Voltage | VIH | 1.4 | V | VIN = VIN-Min to VIN-Max | 5 | ||
| EN Input Current | IEN | -1 | 1 | μA | VIN = 0V or VIN-Max | 5 | |
| Thermal Resistance Junction-to-Ambient SOT25 | θJA | 190 | °C/W | Note 6: device mounted on FR-4 substrate PCB, minimum recommended pad layout, 2oz copper, single sided | 5 |
CAD (KiCad official)
- Symbol:
AP7311-18WG-7 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-25 (KiCad packages3D, STEP)
- 3D model files:
ap7311-18wg-7-etched.step/ap7311-18wg-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ap7311-18wg-7.step/ap7311-18wg-7.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
ap7311-18wg-7.step |
85 KB | You want the bare part, or you mark your own boards. |
ap7311-18wg-7-etched.step |
1.9 MB | You want the part with AP7311-18WG-7 already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 482 faces against 102 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (13 pp, sha256
6bf469c670222d24, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AP7311-18WG-7
**Diodes Incorporated** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-25
AP7311-18WG-7 from Diodes Incorporated, in a SOT-25. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Voltage input pin (2V to 6V, 7V absolute max). Bypass to ground through at least 1uF capacitor. |
| 2 | GND | power_in | Ground reference pin. |
| 3 | EN | input | Enable input, active high. VIH = 1.4V min, VIL = 0.4V max. Referenced to VIN (max VIN + 0.3V). |
| 4 | NC | unconnected | No connection. This pin is unused on the fixed-output variant (AP7311-18WG-7 is a fixed 1.8V output part). |
| 5 | OUT | power_out | Regulated voltage output pin, fixed 1.8V, 150mA max. Bypass to ground through 1uF ceramic capacitor. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25 |
| Category | PMIC |
| Pins | 5 |
## Ordering variants
- `AP7311-18WG-7`
- `AP7311-18WG-7AP7311-WG-7`
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| ESD HBM Human Body Model ESD Protection | ESD HBM | | | 6 | kV | Human Body Model ESD Protection | 4 |
| ESD MM Machine Model ESD Protection | ESD MM | | | 400 | V | Machine Model ESD Protection | 4 |
| Input Voltage | VIN | | | 7 | V | | 4 |
| Operating Junction Temperature Range | TOP | -40 | | 125 | °C | | 4 |
| Storage Temperature Range | TST | -65 | | 150 | °C | | 4 |
| Power Dissipation | PD | | | 640 | mW | SOT25; ratings apply to ambient temperature at 25°C (Note 3) | 4 |
| Maximum Junction Temperature | TJ | | | 150 | °C | | 4 |
| Input voltage | VIN | 2 | | 6 | V | | 4 |
| Output Current | IOUT | 0 | | 150 | mA | Note 4: device maintains stable regulated output without load current | 4 |
| Operating Ambient Temperature | TA | -40 | | 85 | °C | | 4 |
| Input Quiescent Current | IQ | | 55 | 75 | μA | VEN = VIN, IOUT = 0mA | 5 |
| Input Quiescent Current | IQ | | 65 | 85 | μA | VEN = VIN, IOUT = 150mA | 5 |
| Input Shutdown Current | ISHDN | | | 1 | μA | VEN = 0V, IOUT = 0mA | 5 |
| Input Leakage Current | ILEAK | | | 1 | μA | VEN = 0V, OUT grounded | 5 |
| Output Voltage Accuracy | VOUT | -2 | | 2 | % | TA = -40°C to 85°C, IOUT = 30mA | 5 |
| Line Regulation | ΔVOUT/ΔVIN/V | | 0.01 | 0.2 | %/V | VIN = (VOUT +1V) to VIN-Max, VEN = VIN, IOUT = 1mA | 5 |
| Load Regulation | ΔVOUT/VOUT | -0.6 | | 0.6 | % | VIN = (VOUT +1V) to VIN-Max, IOUT from 1mA to 150mA | 5 |
| Current Limit | ILIMIT | 200 | | 300 | mA | VIN = (VOUT +1V) to VIN-Max, VOUT/ROUT = 0.5A | 5 |
| EN Input Logic Low Voltage | VIL | | | 0.4 | V | VIN = VIN-Min to VIN-Max | 5 |
| EN Input Logic High Voltage | VIH | 1.4 | | | V | VIN = VIN-Min to VIN-Max | 5 |
| EN Input Current | IEN | -1 | | 1 | μA | VIN = 0V or VIN-Max | 5 |
| Thermal Resistance Junction-to-Ambient SOT25 | θJA | | 190 | | °C/W | Note 6: device mounted on FR-4 substrate PCB, minimum recommended pad layout, 2oz copper, single sided | 5 |
## CAD (KiCad official)
- Symbol: `AP7311-18WG-7`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-25 (KiCad packages3D, STEP)
- 3D model files: `ap7311-18wg-7-etched.step` / `ap7311-18wg-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ap7311-18wg-7.step` / `ap7311-18wg-7.glb` are the bare package body.
## 3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
| [`ap7311-18wg-7.step`](ap7311-18wg-7.step) | 85 KB | You want the bare part, or you mark your own boards. |
| [`ap7311-18wg-7-etched.step`](ap7311-18wg-7-etched.step) | 1.9 MB | You want the part with `AP7311-18WG-7` already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 482 faces against 102 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://www.diodes.com/assets/Datasheets/AP7311-18WG-7.pdf) (13 pp, sha256 `6bf469c670222d24`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ap7311-18wg-7-datasheet.pdf)