component

AP7176BSP-13

Public Made by Adom

by adom

Diodes Incorporated Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)ap7176bsp-13factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16d ago
viewers ap7176bsp-13: viewers · Ray 16d ago
ap7176bsp-13-etched.glb Publish 0.1.0 · Ray 16d ago
ap7176bsp-13-etched.step ap7176bsp-13: factory component page (tier=lcsc) · Ray 16d ago
ap7176bsp-13-hero.glb ap7176bsp-13: hero GLB from the etched model (keeps the MPN mark) · Ray 16d ago
ap7176bsp-13-hero.overlay.json Publish 0.1.0 · Ray 16d ago
ap7176bsp-13.glb Publish 0.1.0 · Ray 16d ago
ap7176bsp-13.kicad_mod Publish 0.1.0 · Ray 16d ago
ap7176bsp-13.kicad_sym Publish 0.1.0 · Ray 16d ago
ap7176bsp-13.lbr Publish 0.1.0 · Ray 16d ago
ap7176bsp-13.step Publish 0.1.0 · Ray 16d ago
package.json Publish 0.1.0 · Ray 16d ago
page.json Set visibility: public · Ray 16d ago
README.md Publish 0.1.0 · Ray 16d ago

AP7176BSP-13

Diodes Incorporated · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

AP7176BSP-13 from Diodes Incorporated, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PG output Open-drain power-good output that indicates the status of VOUT by monitoring the FB pin, and is pulled low when the voltage is outside the limits, during thermal shutdown, or if VCNTL or VIN goes below its threshold.
2 EN input Enable pin: driving it low disables the part, and when left floating an internal current source pulls it high to enable the part.
3 VIN power_in Power input pin for current supply; connect a decoupling capacitor (≥ 10µF) as close as possible to the pin for noise filtering.
4 VCNTL power_in BIAS supply for the controller, recommended 5V; connect a decoupling capacitor (≥ 1µF) as close as possible to the pin for noise filtering.
5 NC unconnected No connection.
6 VOUT power_out Power output pin.
7 FB input Feedback pin that sets the output voltage via an external resistor divider between VOUT and GND.
8 GND power_in Ground pin; the exposed pad is also connected to GND for good thermal conductivity.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN VIN Supply Voltage (VIN to GND) VIN -0.3 4 V 3
VCNTL VCNTL Supply Voltage (VCNTL to GND) VCNTL -0.3 7 V 3
VOUT to GND Voltage (printed max: VIN +0.3 V, not a fixed number) VOUT -0.3 V 3
PG to GND Voltage -0.3 7 V 3
EN, FB to GND Voltage (printed max: VCNTL +0.3 V, not a fixed number) -0.3 V 3
Power Dissipation (SO-8EP) PD 1.7 W 3
TJ Maximum Junction Temperature TJ 150 °C 3
TSTG Storage Temperature TSTG -65 150 °C 3
TSDR Maximum Lead Soldering Temperature TSDR 260 °C 10 seconds 3
VCNTL VCNTL Supply Voltage VCNTL 3 5.5 V 3
VIN VIN Supply Voltage VIN 1.2 3.65 V 3
VOUT VOUT Output Voltage (printed max: VIN, VDROP, not a fixed number) VOUT 0.8 V VCNTL - VOUT > 1.9V 3
IOUT VOUT Output Current IOUT 0 3 A 3
COUT VOUT Output Capacitance COUT 8 1100 µF IOUT = 3A at 25% nominal VOUT 3
COUT VOUT Output Capacitance COUT 8 1700 µF IOUT = 2A at 25% nominal VOUT 3
COUT VOUT Output Capacitance COUT 8 2400 µF IOUT = 1A at 25% nominal VOUT 3
ESR of VOUT Output Capacitor ESRCOUT 0 200 mΩ 3
TA Ambient Temperature TA -40 85 °C 3
TJ Junction Temperature TJ -40 125 °C 3
VCNTL VCNTL Supply Current IVCNTL 1 1.5 mA EN = VCNTL, IOUT = 0A 3
VCNTL Supply Current at Shutdown ISD 15 30 µA EN = GND 3
VIN Supply Current at Shutdown 1 µA EN = GND, VIN = 3.65V 3
Rising VCNTL POR Threshold VPOR_Rising (VCNTL) 2.5 2.7 2.95 V 3
Rising VIN POR Threshold VPOR_Rising (VIN) 0.8 0.9 1 V 3
Output Voltage Accuracy -1.5 1.5 % VCNTL = 3.0V to 5.5V, IOUT = 0A to 3A, TJ = -40°C to +125°C 4
Load Regulation 0.06 0.25 % IOUT = 0A to 3A 4
Line Regulation -0.15 0.15 %/V IOUT = 10mA, VCNTL = 3.0V to 5.5V 4
FB Input Current -100 100 nA VFB = 0.8V 4
VIN-to-VOUT Dropout Voltage VDROP 0.33 0.38 V VCNTL = 5.0V, IOUT = 3A, VOUT = 2.5V, TJ = +25°C 4
VIN-to-VOUT Dropout Voltage VDROP 0.53 V VCNTL = 5.0V, IOUT = 3A, VOUT = 2.5V, TJ = -40°C to +125°C 4
VIN-to-VOUT Dropout Voltage VDROP 0.31 0.36 V VCNTL = 5.0V, IOUT = 3A, VOUT = 1.8V, TJ = +25°C 4
VIN-to-VOUT Dropout Voltage VDROP 0.5 V VCNTL = 5.0V, IOUT = 3A, VOUT = 1.8V, TJ = -40°C to +125°C 4
VIN-to-VOUT Dropout Voltage VDROP 0.3 0.35 V VCNTL = 5.0V, IOUT = 3A, VOUT = 1.2V, TJ = +25°C 4
VIN-to-VOUT Dropout Voltage VDROP 0.48 V VCNTL = 5.0V, IOUT = 3A, VOUT = 1.2V, TJ = -40°C to +125°C 4
Current-Limit Level ILIM 4.5 5.7 6.7 A TJ = +25°C, VOUT = 80% VNOMINAL 4
Current-Limit Level ILIM 4.2 A TJ = -40°C to +125°C 4
EN Logic High Threshold Voltage EN_HI 0.5 0.8 1.1 V VEN rising 4
Soft-Start Interval tSS 0.3 0.6 1.2 ms 4
Turn-On Delay t_DELAY 200 350 500 µs From being enabled to VOUT rising 10% 4
Rising PG Threshold Voltage VTHPG 90 92 95 % VFB rising 4
PG Pull-Low Voltage VPG_Low 0.25 0.4 V PG sinks 5mA 4
PG Delay Time t_PGDEL 1 2 4 ms From VFB = VTHPG to rising edge of the VPG 4
VCNTL POR Hysteresis VPOR_Hysteresis (VCNTL) 0.4 V 3
VIN POR Hysteresis VPOR_Hys (VIN) 0.5 V 3
Reference Voltage VREF 0.8 V FB = VOUT 4
VOUT Pull-Low Resistance 10 Ω VCNTL = 3.3V, VEN = 0V, VOUT < 0.8V 4
Short Current-Limit Level ISHORT 1.1 A VFB < 0.2V 4
Thermal Shutdown Temperature TSD 170 °C TJ rising 4
Thermal Shutdown Hysteresis TSD_HYS 50 °C 4
EN Hysteresis EN_Hys 0.1 V 4
EN Pull-High Current I_EN 5 µA EN = GND 4
PG Threshold Hysteresis VPG_Hys 8 % 4
PG Debounce Interval tPG_Deb 10 µs VFB < falling PG voltage threshold 4
Thermal Resistance Junction-to-Ambient, SO-8EP θJA 70 C/W Note 6 (device on 2in x 2in FR-4 PCB, 2oz copper) 4
Thermal Resistance Junction-to-Case, SO-8EP θJC 30 C/W Note 6 (device on 2in x 2in FR-4 PCB, 2oz copper) 4

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Terminals: ▪ SO-8EP/MSOP-8EP: Finish, Matte Tin Plated Leads, Solderable per MIL-STD-202, Method 208 14

CAD (KiCad official)

  • Symbol: AP7176BSP-13
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: ap7176bsp-13-etched.step / ap7176bsp-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap7176bsp-13.step / ap7176bsp-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (15 pp, sha256 fd085987eae46849, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF