component
AP64501SP-13
Public Made by Adomby adom
Diodes Incorporated DC-DC Converters, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAP64501SP-13
Diodes Incorporated · DC-DC Converters · SOIC-8-EP
AP64501SP-13 from Diodes Incorporated, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | input | High-side gate drive boost input that supplies the drive for the high-side N-channel power MOSFET, with a 100nF capacitor recommended from BST to SW. |
| 2 | VIN | power_in | Power input that supplies the IC and the step-down power MOSFETs; drive with a 3.8V to 40V source and bypass to GND with a suitably large capacitor. |
| 3 | EN | input | Digital enable input that turns the regulator on when high and off when low, with a precision 1.18V threshold for programming UVLO; connect to VIN or leave floating for automatic startup. |
| 4 | SS | passive | Soft-start pin where a ceramic capacitor from this pin to ground programs the soft-start time, with an internal 4μA current source pulling the SS pin up. |
| 5 | FB | input | Feedback sensing terminal for the output voltage, connected to the output resistive divider (0.8V ±1% reference). |
| 6 | COMP | passive | Compensation pin where an external RC network is connected to adjust the loop response. |
| 7 | GND | power_in | Power ground for the device. |
| 8 | SW | power_out | Power switching output node that supplies power to the output; the output LC filter connects from SW to the load. |
| 9 | EXPOSED PAD | power_in | Heat dissipation path of the die that must be electrically connected to GND and to the PCB ground plane for proper operation and thermal performance. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOIC-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Shutdown Supply Current | ISHDN | 1 | 3 | μA | VEN = 0V | 6 | |
| VIN Undervoltage Rising Threshold | UVLO | 3.5 | 3.7 | V | 6 | ||
| HS Peak Current Limit | IPEAK_LIMIT | 6.8 | 8 | 9.2 | A | Note 8 | 6 |
| Oscillator Frequency | fSW | 510 | 570 | 630 | kHz | 6 | |
| Feedback Voltage | VFB | 792 | 800 | 808 | mV | CCM | 6 |
| EN Logic High Threshold | VEN_H | 1.18 | 1.25 | V | 6 | ||
| EN Logic Low Threshold | VEN_L | 1.03 | 1.09 | V | 6 | ||
| EN Input Current | IEN | 1 | 1.5 | 2 | μA | VEN = 1V | 6 |
| Supply Voltage | VIN | 3.8 | 40 | V | 5 | ||
| Output Voltage | VOUT | 0.8 | 39 | V | 5 | ||
| Operating Ambient Temperature Range | TA | -40 | 85 | °C | 5 | ||
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | 5 | ||
| VIN Supply Pin Voltage | VIN | -0.3 | 42 | V | DC | 5 | |
| VIN Supply Pin Voltage | VIN | -0.3 | 45 | V | 400ms | 5 | |
| Enable/UVLO Pin Voltage | VEN | -0.3 | 42 | V | 5 | ||
| Soft-Start Pin Voltage | VSS | -0.3 | 6 | V | 5 | ||
| Feedback Pin Voltage | VFB | -0.3 | 6 | V | 5 | ||
| Compensation Pin Voltage | VCOMP | -0.3 | 6 | V | 5 | ||
| Storage Temperature | TST | -65 | 150 | °C | 5 | ||
| Junction Temperature | TJ | 160 | °C | 5 | |||
| Lead Temperature | TL | 260 | °C | 5 | |||
| ESD Human Body Model | HBM | 2000 | V | HBM | 5 | ||
| ESD Charged Device Model | CDM | 500 | V | CDM | 5 | ||
| Junction to Ambient Thermal Resistance | θJA | 45 | °C/W | SO-8EP, Note 6 | 5 | ||
| Junction to Case Thermal Resistance | θJC | 5 | °C/W | SO-8EP | 5 |
CAD (KiCad official)
- Symbol:
AP64501SP-13 - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOIC-8-EP (KiCad packages3D, STEP)
- 3D model files:
ap64501sp-13-etched.step/ap64501sp-13-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ap64501sp-13.step/ap64501sp-13.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (26 pp, sha256
a309e45521358952, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).