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Contents

README

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AP3981CS-13

Diodes Incorporated · AC-DC Controllers & Regulators · SO-8

AP3981CS-13 from Diodes Incorporated, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground of the IC.
2 FB input Connects to the auxiliary winding through a divider network; multi-function pin for output voltage sampling (CV control, 2.4V threshold), tONS detection for CC control, line voltage sense for line compensation, and FB-negative-protection detection; absolute maximum -0.3 to 8V.
3 VCC power_in Power supply of the IC; recommended operating range 10 to 28V, absolute maximum -0.3 to 35V.
4 SOURCE passive Source terminal of the integrated MOSFET, connected to the current sense resistor for primary peak current sensing; absolute maximum -0.3 to 8V.
5 DRAIN passive Drain terminal of the integrated 650V MOSFET, tied together with pins 6, 7 and 8.
6 DRAIN passive Drain terminal of the integrated 650V MOSFET, tied together with pins 5, 7 and 8.
7 DRAIN passive Drain terminal of the integrated 650V MOSFET, tied together with pins 5, 6 and 8.
8 DRAIN passive Drain terminal of the integrated 650V MOSFET, tied together with pins 5, 6 and 7.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SO-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Startup Threshold VTH_ST 14.5 16 17.5 V TA=+25°C, VCC=15V 5
Minimum Operating Voltage VOPR(MIN) 6.1 6.8 7.5 V TA=+25°C, VCC=15V 5
Startup Current IST 1 3 µA VCC=VTH_ST-1V before Startup 5
Minimum Operating Current ICC_OPR 450 550 650 µA Static Current 5
Peak Current Sense Threshold Voltage VCS_H 560 630 700 mV 40% to 100% CC Load 5
Peak Current Sense Threshold Voltage VCS_L 160 180 200 mV No Load to 2% CC Load 5
Built-In Line Compensation Resistance RLINE 45 55 65 Ω 5
Leading Edge Blanking tLEB 370 470 570 ns 5
Feedback Threshold Voltage VFB 2.35 2.4 2.45 V Closed Loop Test of VOUT 5
Sample Ratio RatioSAMPLE_L 45 50 55 % No Load to 2% CC Load 5
Sample Ratio RatioSAMPLE_H 75 80 85 % 40% to 100% CC Load 5
VCS Modulation ΔVCS/VCS 1.5 2 2.5 % 10% Load to Full Load 5
Valid Off Time of Valley-On tVAL-ON 26 32 38 µs From the End of tONS 5
Maximum Off Time tOFF(MAX) 1.8 2 2.2 ms 5
Over Voltage Protection at FB Pin VFB(SOVP) 3.3 3.6 3.9 V 5
Under Voltage Protection at FB Pin VFB(SUVP) 1.22 1.35 1.48 V 5
Delay Time of SUVP tDELAY(SUVP) 116 128 140 ms 5
Output Short Protection at FB Pin VFB(SCP) 680 750 820 mV 5
Delay Time of SCP tDELAY(SCP) 58 64 70 ms 5
Over Voltage Protection at VCC Pin VCC(OVP) 29.5 32 34.5 V 5
Maximum Turn-ON Time tONP(MAX) 12 16 20 µs 5
Minimum Peak Current Sense Voltage VCS(MIN) 120 150 180 mV at tONP=4µs 5
Maximum CS Voltage VCS(MAX) 720 800 880 mV 5
Low Threshold for FB Negative Voltage Protection VFB_NEG_L 11 14 17 mV 6
High Threshold for FB Negative Voltage Protection VFB_NEG_H 27 36 45 mV 6
Shutdown Temperature TOTP 130 145 160 °C 6
Temperature Hysteresis THYS 27 30 33 °C 6
Integrated MOSFET Drain-Source Break-Down Voltage BVDSS 650 V 6
Static Drain-Source On-Resistance RDS(ON) 2.8 3.5 Ω 6
Continuous Drain Current ID 3 A 6
Supply Voltage VCC 10 28 V 4
Ambient Temperature TA -40 85 °C 4
Supply Voltage VCC -0.3 35 V 4
SOURCE Input Voltage VSOURCE -0.3 8 V 4
FB Input Voltage VFB -0.3 8 V 4
Drain-Source Voltage VDS 650 V TJ=+25°C 4
Operating Junction Temperature TJ -40 150 °C 4
Storage Temperature TSTG -65 150 °C 4
Lead Temperature TLEAD 300 °C Soldering, 10s 4
ESD (Human Body Model) 2000 V 4
ESD (Charged Device Model) 1000 V 4
Thermal Resistance (Junction to Case) θJC 3 °C/W FR-4, 2oz copper, 1inch2 cooling area 4
Thermal Resistance (Junction to Ambient) θJA 65 °C/W FR-4, 2oz copper, 1inch2 cooling area 4
Below SUVP tONS/tSW tONS/tSW 0.75 Tested @ VFB=1V 5
Above SUVP tONS/tSW tONS/tSW 0.5 Tested @ VFB=2V 5
Fixed Cable Compensation Ratio VCABLE/VOUT 4 % 5

CAD (KiCad official)

  • Symbol: AP3981CS-13
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: ap3981cs-13-etched.step / ap3981cs-13-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap3981cs-13.step / ap3981cs-13.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (16 pp, sha256 1cdae1ba8e2350ca, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF