component
AP22811BW5-7
Public Made by Adomby adom
Diodes Incorporated Power Distribution Switches, SOT-25-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AP22811BW5-7
Diodes Incorporated · Power Distribution Switches · SOT-25-5
AP22811BW5-7 from Diodes Incorporated, in a SOT-25-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Voltage output pin; connect a 0.1µF bypass capacitor and a high-value capacitor (at least 10µF in USB applications) between OUT and GND close to the IC. |
| 2 | GND | power_in | Ground pin of the circuitry. |
| 3 | FLG | output | Open-drain fault report output that goes active low after a nominal 6ms deglitch when an over-current or over-temperature condition occurs; it stays low until both conditions are removed, with RFLG of 40Ω typical and 60Ω maximum at 10mA. |
| 4 | EN/EN | input | Enable input for the AP22811B, which is active low; VIH is at least 1.5V and VIL is no higher than 0.5V, and the pin should not be left floating. |
| 5 | IN | power_in | Voltage input pin; connect a 1µF low-ESR capacitor to GND close to the IC, with an operating input range of 2.7V to 5.5V and an absolute maximum of -0.3V to 6.0V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2.7 | 5.5 | V | 3 | ||
| Output Current | IOUT | 0 | 2 | A | 3 | ||
| EN/EN Input Logic Low Voltage | VIL | 0 | 0.5 | V | 3 | ||
| EN/EN Input Logic High Voltage | VIH | 1.5 | V | 3 | |||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| ESD Human Body Model Protection | ESD HBM | 2000 | V | 3 | |||
| ESD Machine Model Protection | ESD MM | 200 | V | 3 | |||
| Input Voltage | VIN | -0.3 | 6 | V | 3 | ||
| Output Voltage | VOUT | -0.3 | V | Printed as -0.3 to (VIN +0.3) | 3 | ||
| Enable Voltage | VEN/EN | -0.3 | V | Printed as -0.3 to (VIN +0.3) | 3 | ||
| Maximum Junction Temperature | TJ(max) | 150 | °C | 3 | |||
| Storage Temperature | TST | -65 | 150 | °C | 3 | ||
| Input UVLO (VIN rising) | VUVLO | 1.6 | 2 | 2.4 | V | VIN Rising | 4 |
| Input Shutdown Current | ISHDN | 1 | µA | Disabled, OUT = Open | 4 | ||
| Input Leakage Current | ILEAK | 1 | µA | Disabled, OUT Grounded | 4 | ||
| Reverse Leakage Current | IREV | 1 | µA | Disabled, VIN = 0V, VOUT = 5V, IREV at VIN | 4 | ||
| Switch On-Resistance | RDS(ON) | 50 | 65 | mΩ | VIN = 5V, IOUT = 1A, TA = +25°C | 4 | |
| Switch On-Resistance | RDS(ON) | 60 | 90 | mΩ | VIN = 3.3V, IOUT = 1A, TA = +25°C | 4 | |
| Over Load Current Limit | ILIMIT | 2.2 | 2.7 | 3.2 | A | VIN = 5V, VOUT = 4.5V | 4 |
| EN/EN Input Logic Low Voltage | VIL | 0.5 | V | VIN = 2.7V to 5.5V | 4 | ||
| EN/EN Input Logic High Voltage | VIH | 1.5 | V | VIN = 2.7V to 5.5V | 4 | ||
| EN/EN Input Leakage | ILEAK-EN/EN | 0.01 | 1 | µA | VIN = 5V, VEN/EN = 0V and 5.5V | 4 | |
| Output Leakage Current | ILEAK-O | 0.5 | 1 | µA | Disabled, VOUT = 0V | 4 | |
| Output Turn-On Rise Time | tR | 1 | 2.1 | 3.5 | ms | CL = 4.7µF, RLOAD = 10Ω @ VIN = 3.3V, Figure 1 | 4 |
| FLG Output FET On-Resistance | RFLG | 40 | 60 | Ω | IFLG = 10mA | 4 | |
| FLG Off Current | IFOH | 0.01 | 1 | µA | VFLG = 5V | 4 | |
| FLG Blanking Time | tBLANK | 2 | 6 | 13 | ms | Assertion or deassertion due to overcurrent and over-temperature condition | 4 |
| Discharge Resistance | RDIS | 90 | 130 | Ω | VIN = 5V, Disabled, IOUT = 1mA | 4 | |
| Reverse-Voltage Comparator Trip Point | VRVP | 25 | 50 | 75 | mV | VOUT - VIN | 4 |
| Time from Reverse-Voltage Condition to MOSFET Turn off | tTRIG | 2 | 6 | 13 | ms | VIN | 4 |
| Thermal Resistance, Junction to Ambient (SOT25) | RθJA | 123 | °C/W | SOT25, Note 6: four-layer high thermal conductivity board per JEDEC 51-7, TA = +25°C | 3 | ||
| Thermal Resistance, Junction to Case (SOT25) | RθJC | 33 | °C/W | SOT25, Note 6: four-layer high thermal conductivity board per JEDEC 51-7, TA = +25°C | 3 |
CAD (KiCad official)
- Symbol:
AP22811BW5-7 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-25-5 (KiCad packages3D, STEP)
- 3D model files:
ap22811bw5-7-etched.step/ap22811bw5-7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ap22811bw5-7.step/ap22811bw5-7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Diodes Incorporated datasheet (17 pp, sha256
61f1341dcf37060d, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AP22811BW5-7
**Diodes Incorporated** · Power Distribution Switches · SOT-25-5
AP22811BW5-7 from Diodes Incorporated, in a SOT-25-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Voltage output pin; connect a 0.1µF bypass capacitor and a high-value capacitor (at least 10µF in USB applications) between OUT and GND close to the IC. |
| 2 | GND | power_in | Ground pin of the circuitry. |
| 3 | FLG | output | Open-drain fault report output that goes active low after a nominal 6ms deglitch when an over-current or over-temperature condition occurs; it stays low until both conditions are removed, with RFLG of 40Ω typical and 60Ω maximum at 10mA. |
| 4 | EN/EN | input | Enable input for the AP22811B, which is active low; VIH is at least 1.5V and VIL is no higher than 0.5V, and the pin should not be left floating. |
| 5 | IN | power_in | Voltage input pin; connect a 1µF low-ESR capacitor to GND close to the IC, with an operating input range of 2.7V to 5.5V and an absolute maximum of -0.3V to 6.0V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Diodes Incorporated |
| Package | SOT-25-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage | VIN | 2.7 | | 5.5 | V | | 3 |
| Output Current | IOUT | 0 | | 2 | A | | 3 |
| EN/EN Input Logic Low Voltage | VIL | 0 | | 0.5 | V | | 3 |
| EN/EN Input Logic High Voltage | VIH | 1.5 | | | V | | 3 |
| Operating Ambient Temperature | TA | -40 | | 85 | °C | | 3 |
| ESD Human Body Model Protection | ESD HBM | | | 2000 | V | | 3 |
| ESD Machine Model Protection | ESD MM | | | 200 | V | | 3 |
| Input Voltage | VIN | -0.3 | | 6 | V | | 3 |
| Output Voltage | VOUT | -0.3 | | | V | Printed as -0.3 to (VIN +0.3) | 3 |
| Enable Voltage | VEN/EN | -0.3 | | | V | Printed as -0.3 to (VIN +0.3) | 3 |
| Maximum Junction Temperature | TJ(max) | | | 150 | °C | | 3 |
| Storage Temperature | TST | -65 | | 150 | °C | | 3 |
| Input UVLO (VIN rising) | VUVLO | 1.6 | 2 | 2.4 | V | VIN Rising | 4 |
| Input Shutdown Current | ISHDN | | | 1 | µA | Disabled, OUT = Open | 4 |
| Input Leakage Current | ILEAK | | | 1 | µA | Disabled, OUT Grounded | 4 |
| Reverse Leakage Current | IREV | | | 1 | µA | Disabled, VIN = 0V, VOUT = 5V, IREV at VIN | 4 |
| Switch On-Resistance | RDS(ON) | | 50 | 65 | mΩ | VIN = 5V, IOUT = 1A, TA = +25°C | 4 |
| Switch On-Resistance | RDS(ON) | | 60 | 90 | mΩ | VIN = 3.3V, IOUT = 1A, TA = +25°C | 4 |
| Over Load Current Limit | ILIMIT | 2.2 | 2.7 | 3.2 | A | VIN = 5V, VOUT = 4.5V | 4 |
| EN/EN Input Logic Low Voltage | VIL | | | 0.5 | V | VIN = 2.7V to 5.5V | 4 |
| EN/EN Input Logic High Voltage | VIH | 1.5 | | | V | VIN = 2.7V to 5.5V | 4 |
| EN/EN Input Leakage | ILEAK-EN/EN | | 0.01 | 1 | µA | VIN = 5V, VEN/EN = 0V and 5.5V | 4 |
| Output Leakage Current | ILEAK-O | | 0.5 | 1 | µA | Disabled, VOUT = 0V | 4 |
| Output Turn-On Rise Time | tR | 1 | 2.1 | 3.5 | ms | CL = 4.7µF, RLOAD = 10Ω @ VIN = 3.3V, Figure 1 | 4 |
| FLG Output FET On-Resistance | RFLG | | 40 | 60 | Ω | IFLG = 10mA | 4 |
| FLG Off Current | IFOH | | 0.01 | 1 | µA | VFLG = 5V | 4 |
| FLG Blanking Time | tBLANK | 2 | 6 | 13 | ms | Assertion or deassertion due to overcurrent and over-temperature condition | 4 |
| Discharge Resistance | RDIS | | 90 | 130 | Ω | VIN = 5V, Disabled, IOUT = 1mA | 4 |
| Reverse-Voltage Comparator Trip Point | VRVP | 25 | 50 | 75 | mV | VOUT - VIN | 4 |
| Time from Reverse-Voltage Condition to MOSFET Turn off | tTRIG | 2 | 6 | 13 | ms | VIN | 4 |
| Thermal Resistance, Junction to Ambient (SOT25) | RθJA | | 123 | | °C/W | SOT25, Note 6: four-layer high thermal conductivity board per JEDEC 51-7, TA = +25°C | 3 |
| Thermal Resistance, Junction to Case (SOT25) | RθJC | | 33 | | °C/W | SOT25, Note 6: four-layer high thermal conductivity board per JEDEC 51-7, TA = +25°C | 3 |
## CAD (KiCad official)
- Symbol: `AP22811BW5-7`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-25-5 (KiCad packages3D, STEP)
- 3D model files: `ap22811bw5-7-etched.step` / `ap22811bw5-7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ap22811bw5-7.step` / `ap22811bw5-7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Diodes Incorporated datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588941990435672064) (17 pp, sha256 `61f1341dcf37060d`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ap22811bw5-7-datasheet.pdf)