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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs ap22652w6-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 1mo ago
ap22652w6-7-etched.fit.json ap22652w6-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ap22652w6-7-etched.glb ap22652w6-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ap22652w6-7-etched.step ap22652w6-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 3d ago
ap22652w6-7.glb Publish 0.1.0 · Ray 1mo ago
ap22652w6-7.kicad_mod Publish 0.1.0 · Ray 1mo ago
ap22652w6-7.kicad_sym Publish 0.1.0 · Ray 1mo ago
ap22652w6-7.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 6 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray 1mo ago
ap22652w6-7.step Publish 0.1.0 · Ray 1mo ago
package.json Publish 0.2.0 · Ray 1mo ago
pads.json page.json: drop the phantom "PAD" pin. The datasheet package drawing is a 6-lead SOT-26 with 6 pads and no thermal pad, matching the shipped footprint exactly, so there is no exposed pad for this entry to describe and no symbol pin could ever resolve to it. Removed rather than "fixed" by adding a pad: putting copper under a part whose die has no thermal path would be the real defect. · Ray 1mo ago
page.json Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray 12d ago
README.md ap22652w6-7: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 18d ago

AP22652W6-7

Diodes Incorporated · AC-DC Controllers and Regulators · SOT-26

AP22652W6-7 from Diodes Incorporated, in a SOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT power_out Switched voltage output. Connect a 0.1 uF bypass capacitor and a high-value bulk capacitor (at least 10 uF in USB applications, e.g. 120 uF for USB VBUS compliance) close to the pin.
2 ILIM output Current-limit programming pin. Connect an external resistor RLIM from ILIM to GND (10 kOhm <= RLIM <= 210 kOhm) to set the current-limit threshold (125 mA to 2665 mA). Max source current 1 mA.
3 FAULT output Active-low open-drain fault flag. Asserted low during over-current, over-temperature, or reverse-voltage conditions. Requires an external pull-up (e.g. 10 kOhm). Continuous sink current up to 25 mA (10 mA recommended).
4 EN input Active-low enable input for the AP22652/AP22652A. Logic low turns the power switch ON; logic high (or float above VIH) disables the switch and initiates output discharge. VIH = 1.5 V to VIN, VIL = 0 to 0.4 V. Do not leave floating.
5 GND power_in Ground reference. Also tie the exposed pad to this net externally.
6 IN power_in Input supply (3.0 V to 5.5 V). Connect a 0.1 uF or greater ceramic decoupling capacitor from IN to GND as close to the IC as possible. Absolute max 6.0 V.
PAD EP power_in Exposed thermal pad. Internal connection to GND; must be soldered to a GND copper pour externally for improved power dissipation. Not to be used as an electrical ground conduction path.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-26
Category PMIC
Pins 7

Ordering variants

  • AP22652W6-7
  • AP22652W6-7AP22653W6-7
  • AP22652W6-7AP22652AW6-7
  • AP22652W6-7AP22653AW6-7
  • AP22652W6-7AP22652FDZ-7
  • AP22652W6-7AP22653FDZ-7
  • AP22652W6-7AP22652AFDZ-7
  • AP22652W6-7AP22653AFDZ-7

CAD (KiCad official)

  • Symbol: AP22652W6-7
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-26 (KiCad packages3D, STEP)
  • 3D model files: ap22652w6-7-etched.step / ap22652w6-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap22652w6-7.step / ap22652w6-7.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
ap22652w6-7.step 97 KB You want the bare part, or you mark your own boards.
ap22652w6-7-etched.step 2.1 MB You want the part with AP22652W6-7 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 509 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (17 pp, sha256 37551442d8da9325, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF