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AP2263D

Public Made by Adom

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JSMSEMI Battery Management ICs, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AP2263D

JSMSEMI · Battery Management ICs · DIP-8

AP2263D from JSMSEMI, in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GATE output Totem-pole gate drive output for the power MOSFET with 300mA drive capability, clamped at 16V.
2 VDD power_in Chip DC power supply pin, recommended 10 to 26V, absolute maximum 27V, with UVLO and over voltage clamp.
3 NC unconnected No connect pin.
4 SENSE input Current sense input pin with cycle-by-cycle current limit, 0.9V over current threshold and 250ns leading-edge blanking, -0.3 to 7V.
5 NC unconnected Pin 5 is drawn with no label in the pin assignment drawing; assumed no connect.
6 NC unconnected No connect pin.
7 FB input Feedback input pin that sets PWM duty and burst mode (1.2V burst mode voltage), -0.3 to 7V.
8 GND power_in Ground.

Key specifications

Parameter Value
Manufacturer JSMSEMI
Package DIP-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Oscillation frequency, normal Fosc 60 65 70 Khz 7
Frequency modulation range / base frequency Δf_OSC -5 5 % 7
VDD start up current Idd_startup 3 15 uA VDD=12.5V 6
Frequency temperature stability Δf_temp 5 % VDD=16V, TA=-20℃ to 100℃ 7
Frequency voltage stability Δf VDD 5 % VDD=12V to 25V 7
VDD operation current Idd 2.3 mA VDD=16V, FB=3V 6
UVLO enter UVLO(ON) 7.8 V 6
UVLO exit UVLO(OFF) 13.4 V 6
VDD clamp voltage VDD_clamp 32 V Idd=10mA 6
PWM input gain AVCS 2 V/V ΔVFB/ΔVSENSE 6
VFB open loop voltage VFB_open 5.7 V 6
FB pin short current IFB short 0.9 mA Short FB pin to GND and measure current 6
Burst mode voltage 1.2 V 6
Power limiting FB threshold voltage VTH PL 3.7 V 6
Power limiting delay time TD PL 120 mS 6
Maximum duty cycle DC MAX 75 % VDD=18V, SENSE=0V, FB=3V 6
Leading-edge blanking time T_blanking 250 nS 7
SENSE input impedance ZSENSE IN 40 KΩ 7
Over current threshold voltage VTH sense 0.9 V 7
Burst mode base frequency Fosc BM 20 Khz 7
Output low level VOL 0.8 V VDD=16V, IO=-20mA 7
Output high level VOH 10 V VDD=16V, IO=20mA 7
Output clamp voltage level V_Clamp 16 V 7
Output rising time Tr 220 nS VDD=16V, CL=1nF 7
Output falling time Tf 70 nS VDD=16V, CL=1nF 7
Supply Voltage VDD 10 26 V 6
Operating Ambient Temperature TOA -20 85 ℃ 6
ESD Human Model ESD-HM 2 KV 6
ESD Machine Model ESD-MM 150 V 6
VDD supply voltage VDD 27 V 5
VDD clamp voltage 29 V 5
VDD clamp current 10 mA 5
VFB input voltage VFB -0.3 7 V 5
VSENSE input voltage to SENSE pin VSENSE -0.3 7 V 5
Operating junction temperature -55 150 ℃ Min/Max 5
Operating ambient temperature -20 85 ℃ 5
Thermal resistance, Junction to ambient 250 ℃/W 5

CAD (KiCad official)

  • Symbol: AP2263D
  • Footprint: Package_DIP:DIP-8_W7.62mm
  • 3D model: DIP-8 (KiCad packages3D, STEP)
  • 3D model files: ap2263d-etched.step / ap2263d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap2263d.step / ap2263d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JSMSEMI datasheet (12 pp, sha256 8a7a72574048f950, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF