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Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	ap2161wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
viewers	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
ap2161wg-7-etched.fit.json	ap2161wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
ap2161wg-7-etched.glb	ap2161wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
ap2161wg-7-etched.step	ap2161wg-7: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray	3d ago
ap2161wg-7.glb	Publish 0.1.0 · Ray	1mo ago
ap2161wg-7.kicad_mod	Publish 0.1.0 · Ray	1mo ago
ap2161wg-7.kicad_sym	Publish 0.1.0 · Ray	1mo ago
ap2161wg-7.lbr	rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect and oval pad as a SQUARE EAGLE smd; this carries the real pad shape across (0 -> 5 rounded pads) and stops dropping geometry drawn on KiCad User.N layers. Attributes, connects, pads and the pin-1 marker are gated against decreasing and are unchanged. · Ray	1mo ago
ap2161wg-7.step	Publish 0.1.0 · Ray	1mo ago
package.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
pads.json	pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray	1mo ago
page.json	Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout") · Ray	12d ago
README.md	ap2161wg-7: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray	18d ago

AP2161WG-7

Diodes Incorporated · AC-DC Controllers and Regulators · SOT-23-5

AP2161WG-7 from Diodes Incorporated, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT	power_out	Switched voltage output pin. Delivers power to the load through the internal high-side power MOSFET (RDS(on) ≈ 95 mΩ typ). Recommended maximum continuous load current 1.0 A; internal current limit 1.5 A typ.
2	GND	power_in	Device ground reference.
3	FLG	output	Open-drain overcurrent / over-temperature fault report. Asserts active-low when a fault (over-current or thermal shutdown) is triggered, with a 7 ms typical blanking time. Requires an external pull-up resistor (e.g. 10 kΩ). FLG output FET on-resistance ≈ 20 Ω typ at IFLG = 10 mA.
4	EN	input	Enable input. Active-low on AP2161: drive low to turn the switch ON, high to turn OFF. VIL ≤ 0.8 V, VIH ≥ 2.0 V. EN input leakage ≤ 1 µA at VEN = 5 V.
5	IN	power_in	Input voltage pin. Operating range 2.7 V to 5.5 V; absolute maximum 6.5 V. Input UVLO ≈ 1.9 V typ. Input quiescent current 45 µA typ (enabled), shutdown current 0.5 µA typ.

Key specifications

Parameter	Value
Manufacturer	Diodes Incorporated
Package	SOT-23-5
Category	PMIC
Pins	5

Ordering variants

AP2161WG-7
AP2161WG-7SG-13
AP2161WG-7MPG-13
AP2161WG-7FMG-7

CAD (KiCad official)

Symbol: AP2161WG-7
Footprint: Package_TO_SOT_SMD:SOT-23-5
3D model: SOT-23-5 (KiCad packages3D, STEP)
3D model files: ap2161wg-7-etched.step / ap2161wg-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ap2161wg-7.step / ap2161wg-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Diodes Incorporated datasheet (18 pp, sha256 7043c173f072fb1d, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF