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AO4884

Public Made by Adom

by adom

UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 23d ago
viewers ao4884: viewers · Ray 23d ago
ao4884-etched.glb ao4884: factory component page (tier=lcsc) · Ray 23d ago
ao4884-etched.step ao4884: factory component page (tier=lcsc) · Ray 23d ago
ao4884-hero.glb ao4884: hero GLB from the etched model (keeps the MPN mark) · Ray 23d ago
ao4884-hero.overlay.json Publish 0.1.0 · Ray 23d ago
ao4884.glb Publish 0.1.0 · Ray 23d ago
ao4884.kicad_mod Publish 0.1.0 · Ray 23d ago
ao4884.kicad_sym Publish 0.1.0 · Ray 23d ago
ao4884.lbr Publish 0.1.0 · Ray 23d ago
ao4884.step Publish 0.1.0 · Ray 23d ago
package.json Publish 0.1.0 · Ray 23d ago
page.json ao4884: specified limits as data (metadata.characteristics, 25 rows from the datasheet) · Ray 17d ago
README.md ao4884: specified limits as data (metadata.characteristics, 25 rows from the datasheet) · Ray 17d ago

AO4884

UMW · MOSFETs · SOP-8

AO4884 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of N-channel MOSFET 1; the pinning table assigns pins 1 and 3 to SOURCE (S1, S2).
2 G1 input Gate terminal of N-channel MOSFET 1; the pinning table assigns pins 2 and 4 to GATE (G1, G2).
3 S2 passive Source terminal of N-channel MOSFET 2; the pinning table assigns pins 1 and 3 to SOURCE (S1, S2).
4 G2 input Gate terminal of N-channel MOSFET 2; the pinning table assigns pins 2 and 4 to GATE (G1, G2).
5 D2 passive Drain terminal of the MOSFET pair; the pinning table assigns pins 5 to 8 to DRAIN (D1, D2), with the per-pin D1/D2 mapping not stated explicitly.
6 D2 passive Drain terminal of the MOSFET pair; the pinning table assigns pins 5 to 8 to DRAIN (D1, D2), with the per-pin D1/D2 mapping not stated explicitly.
7 D1 passive Drain terminal of the MOSFET pair; the pinning table assigns pins 5 to 8 to DRAIN (D1, D2), with the per-pin D1/D2 mapping not stated explicitly.
8 D1 passive Drain terminal of the MOSFET pair; the pinning table assigns pins 5 to 8 to DRAIN (D1, D2), with the per-pin D1/D2 mapping not stated explicitly.

Key specifications

Parameter Value
Manufacturer UMW
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage BVDSS 40 V ID=250µA, VGS=0V 3
Gate-Body leakage current IGSS -100 100 nA VDS=0V, VGS=±20V 3
Gate Threshold Voltage VGS(th) 1.2 1.7 2.5 V VDS=VGS, ID=250μA 3
On state drain current ID(ON) 50 A VGS=10V, VDS=5V 3
Static Drain-Source On-Resistance RDS(ON) 13 mΩ VGS=10V 1
Static Drain-Source On-Resistance RDS(ON) 16 mΩ VGS=4.5V 1
Forward Transconductance gFS 27.2 S VDS=5V, ID=10A 3
Diode Forward Voltage VSD 0.7 1 V IS=1A, VGS=0V 3
Input Capacitance Ciss 1200 1500 1950 pF VGS=0V, VDS=20V, f=1MHz 3
Output Capacitance Coss 150 215 280 pF VGS=0V, VDS=20V, f=1MHz 3
Reverse Transfer Capacitance Crss 80 135 190 pF VGS=0V, VDS=20V, f=1MHz 3
Gate resistance Rg 1.5 3.5 5.3 Ω VGS=0V, VDS=0V, f=1MHz 3
Drain-Source Voltage VDS 40 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 10 A TA=25°C 1
Continuous Drain Current ID 8 A TA=70°C 1
Pulsed Drain Current IDM 50 A 1
Avalanche Current IAS, IAR 35 A 1
Avalanche energy EAS, EAR 61 mJ L=0.1mH 1
Power Dissipation PD 2 W TA=25°C 1
Power Dissipation PD 1.3 W TA=70°C 1
Junction and Storage Temperature Range TJ, TSTG -55 150 °C 1
Maximum Junction-to-Ambient (thermal resistance) RθJA 48 62.5 °C/W t ≤ 10s 2
Maximum Junction-to-Ambient (thermal resistance) RθJA 74 90 °C/W Steady-State 2
Maximum Junction-to-Lead (thermal resistance) RθJL 32 40 °C/W Steady-State 2

CAD (KiCad official)

  • Symbol: AO4884
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ao4884-etched.step / ao4884-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ao4884.step / ao4884.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (11 pp, sha256 bf40a91f9b48050f, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF