component

AO4832

Public Made by Adom

by adom

UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsao4832factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 16d ago
viewers ao4832: viewers · Ray 16d ago
ao4832-etched.glb Publish 0.1.0 · Ray 16d ago
ao4832-etched.step ao4832: factory component page (tier=lcsc) · Ray 16d ago
ao4832-hero.glb ao4832: hero GLB from the etched model (keeps the MPN mark) · Ray 16d ago
ao4832-hero.overlay.json Publish 0.1.0 · Ray 16d ago
ao4832.glb Publish 0.1.0 · Ray 16d ago
ao4832.kicad_mod Publish 0.1.0 · Ray 16d ago
ao4832.kicad_sym Publish 0.1.0 · Ray 16d ago
ao4832.lbr Publish 0.1.0 · Ray 16d ago
ao4832.step Publish 0.1.0 · Ray 16d ago
package.json Publish 0.1.0 · Ray 16d ago
page.json Set visibility: public · Ray 16d ago
README.md Publish 0.1.0 · Ray 16d ago

AO4832

UMW · MOSFETs · SOP-8

AO4832 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive SOURCE terminal of N-channel MOSFET 1; the pinning table lists pins 1 and 3 as SOURCE (S1, S2), and the absolute maximum VGS is ±20V.
2 G1 input GATE of N-channel MOSFET 1; gate-source voltage is rated ±20V absolute maximum.
3 S2 passive SOURCE terminal of N-channel MOSFET 2; the pinning table lists pins 1 and 3 as SOURCE (S1, S2), and the absolute maximum VGS is ±20V.
4 G2 input GATE of N-channel MOSFET 2; gate-source voltage is rated ±20V absolute maximum.
5 D1 passive DRAIN terminal of the dual MOSFET (D1, D2); drain-source voltage is rated 30V.
6 D1 passive DRAIN terminal of the dual MOSFET (D1, D2); drain-source voltage is rated 30V.
7 D2 passive DRAIN terminal of the dual MOSFET (D1, D2); drain-source voltage is rated 30V.
8 D2 passive DRAIN terminal of the dual MOSFET (D1, D2); drain-source voltage is rated 30V.

Key specifications

Parameter Value
Manufacturer UMW
Package SOP-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Breakdown Voltage BVDSS 30 V ID=250µA, VGS=0V 3
Gate-Body leakage current IGSS 100 nA VDS=0V, VGS=±20V 3
Gate Threshold Voltage VGS(th) 1.5 1.9 2.5 V VDS=VGS, ID=250μA 3
On state drain current ID(ON) 55 A VGS=10V, VDS=5V 3
Static Drain-Source On-Resistance RDS(ON) 10.8 13 mΩ VGS=10V, ID=10A 3
Static Drain-Source On-Resistance RDS(ON) 14 17.5 mΩ VGS=4.5V, ID=8A 3
Forward Transconductance gFS 43 S VDS=5V, ID=10A 3
Diode Forward Voltage VSD 0.75 1 V IS=1A, VGS=0V 3
Maximum Body-Diode Continuous Current IS 2.5 A 3
Zero Gate Voltage Drain Current IDSS 1 µA VDS=30V, VGS=0V 3
Zero Gate Voltage Drain Current IDSS 5 µA VDS=30V, VGS=0V, TJ=55°C 3
Input Capacitance Ciss 610 760 910 pF VGS=0V, VDS=15V, f=1MHz 3
Output Capacitance Coss 88 125 160 pF VGS=0V, VDS=15V, f=1MHz 3
Reverse Transfer Capacitance Crss 40 70 100 pF VGS=0V, VDS=15V, f=1MHz 3
Gate resistance Rg 0.8 1.6 2.4 Ω VGS=0V, VDS=0V, f=1MHz 3
Total Gate Charge Qg(10V) 11 14 17 nC VGS=10V, VDS=15V, ID=10A 3
Drain-Source Voltage VDS 30 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current ID 10 A TA=25°C 1
Continuous Drain Current ID 8 A TA=70°C 1
Pulsed Drain Current IDM 55 A 1
Avalanche Current IAS, IAR 22 A 1
Avalanche energy EAS, EAR 24 mJ L=0.1mH 1
Power Dissipation PD 2 W TA=25°C 1
Power Dissipation PD 1.3 W TA=70°C 1
Junction and Storage Temperature Range TJ, TSTG -55 150 °C 1
Maximum Junction-to-Ambient RθJA 48 62.5 °C/W t ≤ 10s 2
Maximum Junction-to-Ambient RθJA 74 90 °C/W Steady-State 2
Maximum Junction-to-Lead RθJL 32 40 °C/W Steady-State 2

CAD (KiCad official)

  • Symbol: AO4832
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ao4832-etched.step / ao4832-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ao4832.step / ao4832.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: UMW datasheet (11 pp, sha256 0a57e5ef67d450a6, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF