component
AO4614
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AO4614
UMW · MOSFETs · SOP-8
AO4614 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of the N-channel MOSFET; the N-channel VDS is 40V and the P-channel VDS is -40V, with pin 1 sharing the package with the N-channel drain-source limits in the absolute maximum table. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage is limited to ±20V for both the N-channel and P-channel devices. |
| 3 | S2 | passive | Source terminal of the P-channel MOSFET; the P-channel VDS is -40V and ID is -5A per the absolute maximum table. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage is limited to ±20V for both the N-channel and P-channel devices. |
| 5 | D1 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
| 6 | D1 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
| 7 | D2 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
| 8 | D2 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
AO4614 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ao4614-etched.step/ao4614-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ao4614.step/ao4614.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (13 pp, sha256
29c6909cebe3da37, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AO4614
**UMW** · MOSFETs · SOP-8
AO4614 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source terminal of the N-channel MOSFET; the N-channel VDS is 40V and the P-channel VDS is -40V, with pin 1 sharing the package with the N-channel drain-source limits in the absolute maximum table. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage is limited to ±20V for both the N-channel and P-channel devices. |
| 3 | S2 | passive | Source terminal of the P-channel MOSFET; the P-channel VDS is -40V and ID is -5A per the absolute maximum table. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage is limited to ±20V for both the N-channel and P-channel devices. |
| 5 | D1 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
| 6 | D1 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
| 7 | D2 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
| 8 | D2 | passive | Drain pin shared by the complementary MOSFET drains (D1 and D2 are tied to pins 5 to 8); VDS is 40V for the N-channel and -40V for the P-channel. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `AO4614`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ao4614-etched.step` / `ao4614-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ao4614.step` / `ao4614.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755875295972995072) (13 pp, sha256 `29c6909cebe3da37`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ao4614-datasheet.pdf)