component
AO4409
Public Made by Adomby adom
UMW MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AO4409
UMW · MOSFETs · SOP-8
AO4409 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are internally common source and are to be connected together. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are internally common source and are to be connected together. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are internally common source and are to be connected together. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; the absolute maximum gate-source voltage is ±20 V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
AO4409 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ao4409-etched.step/ao4409-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ao4409.step/ao4409.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: UMW datasheet (8 pp, sha256
87e60d1d8b1d9577, retrieved 2026-10-09, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AO4409
**UMW** · MOSFETs · SOP-8
AO4409 from UMW, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are internally common source and are to be connected together. |
| 2 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are internally common source and are to be connected together. |
| 3 | S | passive | Source terminal of the P-channel MOSFET; pins 1, 2 and 3 are internally common source and are to be connected together. |
| 4 | G | input | Gate terminal of the P-channel MOSFET; the absolute maximum gate-source voltage is ±20 V. |
| 5 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
| 6 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
| 7 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
| 8 | D | passive | Drain terminal of the P-channel MOSFET; pins 5 to 8 are internally common drain and are to be connected together, with VDS limited to -30 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | UMW |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `AO4409`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ao4409-etched.step` / `ao4409-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ao4409.step` / `ao4409.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [UMW datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8755874748117200896) (8 pp, sha256 `87e60d1d8b1d9577`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ao4409-datasheet.pdf)