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AO4407

Public Made by Adom

by adom

JSMSEMI MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 20d ago
viewers ao4407: viewers · Ray 20d ago
ao4407-etched.glb ao4407: factory component page (tier=lcsc) · Ray 20d ago
ao4407-etched.step ao4407: factory component page (tier=lcsc) · Ray 20d ago
ao4407-hero.glb ao4407: hero GLB from the etched model (keeps the MPN mark) · Ray 20d ago
ao4407-hero.overlay.json Publish 0.1.0 · Ray 20d ago
ao4407.glb Publish 0.1.0 · Ray 20d ago
ao4407.kicad_mod Publish 0.1.0 · Ray 20d ago
ao4407.kicad_sym Publish 0.1.0 · Ray 20d ago
ao4407.lbr Publish 0.1.0 · Ray 20d ago
ao4407.step Publish 0.1.0 · Ray 20d ago
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page.json Set visibility: public · Ray 20d ago
README.md Publish 0.1.0 · Ray 20d ago

AO4407

JSMSEMI · MOSFETs · SOP-8

AO4407 from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source terminal of the P-channel MOSFET, labelled S in the SOP-8 top-view pin diagram; the datasheet gives no per-pin voltage or current limit for this pin.
2 S passive Source terminal of the P-channel MOSFET, labelled S in the SOP-8 top-view pin diagram; the datasheet gives no per-pin voltage or current limit for this pin.
3 S passive Source terminal of the P-channel MOSFET, labelled S in the SOP-8 top-view pin diagram; the datasheet gives no per-pin voltage or current limit for this pin.
4 G input Gate terminal of the P-channel MOSFET, labelled G in the SOP-8 top-view pin diagram; the gate-source voltage limit of ±20 V applies to this pin's drive.
5 D passive Drain terminal of the P-channel MOSFET, labelled D in the SOP-8 top-view pin diagram; the drain-source voltage is limited to -30 V.
6 D passive Drain terminal of the P-channel MOSFET, labelled D in the SOP-8 top-view pin diagram; the drain-source voltage is limited to -30 V.
7 D passive Drain terminal of the P-channel MOSFET, labelled D in the SOP-8 top-view pin diagram; the drain-source voltage is limited to -30 V.
8 D passive Drain terminal of the P-channel MOSFET, labelled D in the SOP-8 top-view pin diagram; the drain-source voltage is limited to -30 V.

Key specifications

Parameter Value
Manufacturer JSMSEMI
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: AO4407
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ao4407-etched.step / ao4407-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ao4407.step / ao4407.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JSMSEMI datasheet (6 pp, sha256 979303c7bebef84d, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF