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AO4406

JSMSEMI · MOSFETs · SOP-8

AO4406 from JSMSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S passive Source of the N-channel MOSFET, pins 1-3 are tied together as the source.
2 S passive Source of the N-channel MOSFET, pins 1-3 are tied together as the source.
3 S passive Source of the N-channel MOSFET, pins 1-3 are tied together as the source.
4 G input Gate of the N-channel MOSFET, with a maximum gate-source voltage of ±20 V.
5 D passive Drain of the N-channel MOSFET, rated 30 V VDS, pins 5-8 are tied together as the drain.
6 D passive Drain of the N-channel MOSFET, rated 30 V VDS, pins 5-8 are tied together as the drain.
7 D passive Drain of the N-channel MOSFET, rated 30 V VDS, pins 5-8 are tied together as the drain.
8 D passive Drain of the N-channel MOSFET, rated 30 V VDS, pins 5-8 are tied together as the drain.

Key specifications

Parameter Value
Manufacturer JSMSEMI
Package SOP-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: AO4406
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ao4406-etched.step / ao4406-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ao4406.step / ao4406.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: JSMSEMI datasheet (6 pp, sha256 04817c636bad78f1, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF