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AMT49700KETJTR

Public Made by Adom

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Allegro MicroSystems, LLC New Arrivals, QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentothersamt49700ketjtrfactory-2.0.0extractor-text

Verified AMT49700KETJTR

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AMT49700KETJTR · QFN-32(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 45-page datasheet
  • ✓distributor: lcsc C7214398, digikey 620-2056-2-ND, mouser 250-AMT49700KETJTR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0bbf2j8p/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.44)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ amt49700ketjtr.kicad_sym✓ amt49700ketjtr.kicad_mod✓ amt49700ketjtr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4d ago
viewers amt49700ketjtr: viewers · Ray 4d ago
amt49700ketjtr-etched.glb Publish 0.1.0 · Ray 4d ago
amt49700ketjtr-etched.step amt49700ketjtr: factory component page (tier=lcsc) · Ray 4d ago
amt49700ketjtr-hero.glb amt49700ketjtr: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
amt49700ketjtr-hero.overlay.json Publish 0.1.0 · Ray 4d ago
amt49700ketjtr.glb Publish 0.1.0 · Ray 4d ago
amt49700ketjtr.kicad_mod Publish 0.1.0 · Ray 4d ago
amt49700ketjtr.kicad_sym Publish 0.1.0 · Ray 4d ago
amt49700ketjtr.lbr Publish 0.1.0 · Ray 4d ago
amt49700ketjtr.step Publish 0.1.0 · Ray 4d ago
package.json Publish 0.1.0 · Ray 4d ago
page.json Set visibility: public · Ray 4d ago
README.md Publish 0.1.0 · Ray 4d ago
verification.json Verified: Published by the parts factory: tier lcsc, 33 pins · Ray 4d ago

AMT49700KETJTR

Allegro MicroSystems, LLC · New Arrivals · QFN-32(5x5)

AMT49700KETJTR from Allegro MicroSystems, LLC, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP2 passive Charge pump capacitor terminal; connect a 100 nF (50 V) ceramic capacitor between CP1 and CP2 (abs max -0.3 to VBB + 8 V).
2 NC unconnected No connection (shown as NC in the pinout diagram).
3 VCP passive Charge pump storage capacitor terminal for above-supply high-side drive; connect a 100 nF (16 V) ceramic capacitor between VCP and VBB.
4 NC unconnected No connection (shown as NC in the pinout diagram).
5 RESETn input Standby mode control: a low pulse (tRST) resets faults, held low longer than tRSD forces sleep; can be pulled to VBB with 33 kΩ, abs max -0.3 to 6 V.
6 DIR input Direction logic input with filtered hysteresis; when high the Phase Angle Number increases on the STEP rising edge, no effect when using the serial interface (abs max 6 V).
7 STEP input Step logic input; motor advances on the rising edge, filtered input with hysteresis (abs max 6 V).
8 STRn input Serial strobe (chip select) input; when high, SCK and SDI activity is ignored and SDO is high impedance (abs max 6 V).
9 SCK input Serial clock input; data latched from SDI on the rising edge, 16 rising edges per write, held high when STRn changes (abs max 6 V).
10 SDI input Serial data input, 16-bit word, MSB first (abs max 6 V).
11 SDO tri_state Serial data output, high impedance when STRn is high, outputs the FF fault flag bit as soon as STRn goes low (abs max 6 V).
12 DIAG output Open-drain diagnostic output with function selected via serial interface, default is fault flag; survives up to 40 V but goes high impedance above about 16 V, typically pulled up with 10 kΩ to 20 kΩ.
13 NC unconnected No connection (shown as NC in the pinout diagram).
14 VBB power_in Main motor and chip supply (3.7 to 42 V operation, abs max 42 V); connect both VBB pins together, each decoupled with a low-ESR electrolytic and a ceramic capacitor.
15 NC unconnected No connection (shown as NC in the pinout diagram).
16 OBP output Bridge B positive output for motor phase B; positive current flows from OBP to OBM (abs max -0.3 to VBB).
17 GNDPB power_in Power ground for B phase bridge; must be connected to GND (within ±0.1 V).
18 NC unconnected No connection (shown as NC in the pinout diagram).
19 OBM output Bridge B negative output for motor phase B (abs max -0.3 to VBB).
20 NC unconnected No connection (shown as NC in the pinout diagram).
21 NC unconnected No connection (shown as NC in the pinout diagram).
22 OAM output Bridge A negative output for motor phase A (abs max -0.3 to VBB).
23 NC unconnected No connection (shown as NC in the pinout diagram).
24 GNDPA power_in Power ground for A phase bridge; must be connected to GND (within ±0.1 V).
25 OAP output Bridge A positive output for motor phase A; positive current flows from OAP to OAM (abs max -0.3 to VBB).
26 NC unconnected No connection (shown as NC in the pinout diagram).
27 VBB power_in Main motor and chip supply (3.7 to 42 V operation, abs max 42 V); connect both VBB pins together, each decoupled with a low-ESR electrolytic and a ceramic capacitor.
28 NC unconnected No connection (shown as NC in the pinout diagram).
29 GND power_in Power and reference ground; connect to GNDPA and GNDPB.
30 NC unconnected No connection (shown as NC in the pinout diagram).
31 CP1 passive Charge pump capacitor terminal; connect a 100 nF (50 V) ceramic capacitor between CP1 and CP2 (abs max -0.3 to VBB + 0.3 V).
32 NC unconnected No connection (shown as NC in the pinout diagram).
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package QFN-32(5x5)
Category Others
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Load Supply Voltage VBB -0.3 42 V 3
Terminal DIAG VDIAG -0.3 40 V 3
Terminals STEP, DIR, SCK, SDI, SDO, STRn -0.3 6 V 3
Terminal RESETn VRESETn -0.3 6 V Can be pulled to VBB with 33 kΩ 3
Ground terminals GNDPA, GNDPB VGNDPA -0.1 0.1 V All ground terminals must be connected together 3
Ambient Operating Temperature Range TA -40 150 °C Limited by power dissipation 3
Maximum Continuous Junction Temperature TJ(max) 165 °C 3
Transient Junction Temperature TJt 175 °C Overtemperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours 3
Storage Temperature Range Tstg -55 150 °C 3
Package Thermal Resistance RθJA 30 °C/W High-K PCB (JESD51-7) 3
Supply Voltage Range VBB 0 42 V No unsafe states 6
Supply Voltage Range VBB 5.5 V Outputs driving (max VBBOV) 6
Supply Quiescent Current IBBQ 25 mA DIS = 1 6
Supply Quiescent Current IBBQ 20 40 µA Sleep Mode, VBB = 12 V, GTS = 1, STRn = 1 or VRESETn < 0.5 V, TJ = 25°C 6
Supply Quiescent Current IBBQ 60 100 µA Sleep Mode, VBB = 12 V, GTS = 1, STRn = 1 or VRESETn < 0.5 V, TJ = 150°C 6
Logic I/O Regulator Voltage VLIO 3.1 3.3 3.5 V VLR = 0 6
Logic I/O Regulator Voltage VLIO 4.8 5 5.2 V VLR = 1 6
High-Side On-Resistance RONH 500 600 mΩ VBB ≥ 7 V, IOUT = -1 A, TJ = 25°C 6
High-Side On-Resistance RONH 900 1100 mΩ VBB = 13.5 V, IOUT = -1 A, TJ = 150°C 6
High-Side Body Diode Forward Voltage VFH 1.4 V IF = 1 A 6
High-Side Body Diode Forward Voltage VFH 1.2 V IF = 0.1 A 6
Low-Side On-Resistance RONL 500 600 mΩ VBB ≥ 7 V, IOUT = 1 A, TJ = 25°C, MXI[4:0] = 3…31 6
Low-Side On-Resistance RONL 900 1100 mΩ VBB = 13.5 V, IOUT = 1 A, TJ = 150°C, MXI[4:0] = 3…31 6
Low-Side On-Resistance RONL 1200 1800 mΩ VBB ≥ 7 V, IOUT = 150 mA, TJ = 25°C, MXI[4:0] = 0…2 6
Low-Side On-Resistance RONL 2100 3000 mΩ VBB = 13.5 V, IOUT = 150 mA, TJ = 150°C, MXI[4:0] = 0…2 6
Low-Side Body Diode Forward Voltage VFL 1.4 V IF = -1 A 6
Low-Side Body Diode Forward Voltage VFL 1.2 V IF = -0.1 A 6
Output Leakage Current ILO 65 120 µA GTS = 0, RESETn = 1, DIS = 1, VO = VBB 6
Output Leakage Current ILO -200 -120 µA GTS = 0, RESETn = 1, DIS = 1, VO = 0 V 6
Output Leakage Current ILO 1 20 µA GTS = 1 or VRESETn < 0.5 V, VO = VBB 6
Output Leakage Current ILO -20 1 µA GTS = 1 or VRESETn < 0.5 V, VO = 0 V 6
System Clock Period tOSC 47.5 50 52.5 ns 7
Blank Time tBLANK 3.32 3.5 3.68 µs Default power-up value 7
PWM Frequency fPWM 18.32 19.2 20.24 kHz Default power-up value 7
Bridge PWM Period tPWM 49.4 52 54.6 µs Default power-up value, DS = 0 7
Bridge PWM Dither Dwell Time tDIT 0.95 1 1.05 ms Default power-up value 7
Current Trip Point Error EITrip 10 % MXI[4:0] = 3…31 7
Current Trip Point Error EITrip 15 % MXI[4:0] = 0…2 7
Input Low Voltage VIL 0.3 V max is 0.3 × VLIO 7
Input High Voltage VIH 0.7 V min is 0.7 × VLIO 7
Input Low Voltage for Sleep Mode VILS 0.5 V RESETn input only 7
Input Hysteresis VIHys 100 300 mV 7
Output Low Voltage VOL 0.4 V IOL = 1 mA 7
Output Leakage (SDO) IOSD -1 1 µA 0 V < VO < VLIO, STRn = 1 7
Output Leakage (DIAG) IODI 1 µA 0 V < VO < 9 V 7
Reset Pulse Width tRST 1.5 8 µs 7
Reset Shutdown Pulse Width tRSD 40 µs 7
Wake Up From Sleep tEN 1 ms 7
Interface Ready From Sleep tIR 1.1 ms 7
VBB Overvoltage Threshold VBBOV 32 34 36 V VBB rising 8
VBB Undervoltage Threshold VBBUV 4.7 4.9 5.1 V VBB falling 8
High-Side Overcurrent Threshold IOCH 1.6 2.2 3 A 8
Hot Temperature Warning Threshold TJWH 125 135 145 °C Temperature increasing 8
Overtemperature Shutdown TJF 170 180 °C Temperature increasing 8

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper to the AMT49700 is recommended. All ground terminals must be connected together externally. The copper ground plane located 42

CAD (KiCad official)

  • Symbol: AMT49700KETJTR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: amt49700ketjtr-etched.step / amt49700ketjtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amt49700ketjtr.step / amt49700ketjtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (45 pp, sha256 f40780a7ddc01aa0, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF