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AMT49105KEVTR-J

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Allegro MicroSystems, LLC Gate Drive ICs, QFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AMT49105KEVTR-J

Allegro MicroSystems, LLC · Gate Drive ICs · QFN-48(7x7)

AMT49105KEVTR-J from Allegro MicroSystems, LLC, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VLR power_out VLR is the logic supply regulator output, selectable as 3.3 or 5 V, and requires a ceramic capacitor of at least 1 µF with ESR no more than 250 mΩ to GND for stability.
2 ENABLE input ENABLE disables all gate drive outputs when pulled low in direct mode or after a timeout in watchdog mode.
3 HA input HA is the logic input controlling the high-side gate drive output, with a pull-down connected to the input.
4 LA input LA is the logic input controlling the low-side gate drive output, with a pull-down connected to the input.
5 HB input HB is the logic input controlling the high-side gate drive output, with a pull-down connected to the input.
6 LB input LB is the logic input controlling the low-side gate drive output, with a pull-down connected to the input.
7 HC input HC is the logic input controlling the high-side gate drive output, with a pull-down connected to the input.
8 LC input LC is the logic input controlling the low-side gate drive output, with a pull-down connected to the input.
9 WDOG input WDOG is the external microcontroller window watchdog input with resistor pull-down and programmable minimum and maximum clock period.
10 STRn input STRn is the serial strobe and chip-select input with resistor pull-up; when high, SCK and SDI activity is ignored.
11 SCK input SCK is the serial clock input with resistor pull-down; data is latched in from SDI on the rising edge.
12 SDI input SDI is the serial data input with resistor pull-down accepting a 16-bit serial word, MSB first.
13 SDO output SDO is the serial data output, high impedance or clock output when STRn is high, and outputs the fault flag (Status register bit 15) as soon as STRn goes low.
14 MRSTn output MRSTn is the microcontroller reset output that holds the microcontroller in reset until supplies are available and resets it on watchdog failure.
15 BXM output BXM is the BEMF zero crossing multiplex logic output representing the state of a selected phase relative to the average voltage of the three phases.
16 CSO output CSO is the current sense amplifier output.
17 CSM input CSM is the negative differential current sense amplifier input, connected directly to one end of the sense resistor on a separate PCB trace.
18 CSP input CSP is the positive differential current sense amplifier input, connected directly to the other end of the sense resistor on a separate PCB trace.
19 PM input PM is the program mode logic input that disables the watchdog and MRSTn.
20 LRX output LRX is the LIN or PWM receive logic level output.
21 LTX input LTX is the LIN or FAULT transmit logic level input.
22 LIN bidirectional LIN is the LIN bus connection compliant with ISO17987 (LIN 2.x) and can also be used as a PWM input passed to LRX.
23 GND power_in GND is the analog reference, digital, and power ground; all GND terminals must be connected together to supply ground.
24 GND power_in GND is the analog reference, digital, and power ground; all GND terminals must be connected together to supply ground.
25 LSSC passive LSSC is the low-side return path for discharge of the low-side MOSFET gate capacitance, connected through a low-impedance track to the common source of the phase C low-side MOSFETs.
26 GLC output GLC is the phase C low-side gate-drive output for an external N-channel MOSFET.
27 GHC output GHC is the phase C high-side gate-drive output for an external N-channel MOSFET.
28 SC passive SC is the phase C motor connection that senses the voltage switched across the load and serves as the negative supply for the floating high-side driver.
29 CC power_in CC is the phase C high-side bootstrap capacitor connection and positive supply for the high-side gate driver.
30 LSSB passive LSSB is the low-side return path for discharge of the low-side MOSFET gate capacitance, connected through a low-impedance track to the common source of the phase B low-side MOSFETs.
31 GLB output GLB is the phase B low-side gate-drive output for an external N-channel MOSFET.
32 GHB output GHB is the phase B high-side gate-drive output for an external N-channel MOSFET.
33 SB passive SB is the phase B motor connection that senses the voltage switched across the load and serves as the negative supply for the floating high-side driver.
34 CB power_in CB is the phase B high-side bootstrap capacitor connection and positive supply for the high-side gate driver.
35 LSSA passive LSSA is the low-side return path for discharge of the low-side MOSFET gate capacitance, connected through a low-impedance track to the common source of the phase A low-side MOSFETs.
36 GLA output GLA is the phase A low-side gate-drive output for an external N-channel MOSFET.
37 GHA output GHA is the phase A high-side gate-drive output for an external N-channel MOSFET.
38 SA passive SA is the phase A motor connection that senses the voltage switched across the load and serves as the negative supply for the floating high-side driver.
39 CA power_in CA is the phase A high-side bootstrap capacitor connection and positive supply for the high-side gate driver.
40 VREG power_out VREG is the regulated gate drive supply output, selectable as 8 or 11 V, requiring a storage capacitor of at least 4.7 µF (X7R, 50 V).
41 CP2 passive CP2 is the charge pump capacitor connection; a 470 nF ceramic capacitor is connected between CP1 and CP2.
42 CP1 passive CP1 is the charge pump capacitor connection; a 470 nF ceramic capacitor is connected between CP1 and CP2.
43 GND power_in GND is the analog reference, digital, and power ground; all GND terminals must be connected together to supply ground.
44 VBB power_in VBB is the main power supply input for the internal regulators and charge pump, operating from 5.5 to 50 V and connected through reverse voltage protection.
45 IG input IG is the ignition switch input with resistor pull-down that wakes the device and enables the logic regulator, with input thresholds allowing ±2 V ground difference.
46 BRSW passive BRSW is a switched version of the VBRG voltage, high impedance in sleep mode, which can also be switched off via the serial interface.
47 VBRG input VBRG is the sense input to the top of the external MOSFET bridge for measuring the drain voltage of the high-side MOSFETs.
48 DIAG output DIAG is the programmable diagnostic output that can be shorted to ground or VBB without damage.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package QFN-48(7x7)
Category Power Management
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VBB -0.3 50 V 3
Pumped Regulator Terminal VREG -0.3 16 V 3
Logic Regulator Output VLR -0.3 6 V 3
LIN Bus Interface VLIN -40 50 V 3
Logic Inputs (except IG) -0.3 6 V 3
Logic Input VIG -4 50 V IG 3
Logic Output VDIAG -0.3 50 V DIAG 3
Bridge Drain Monitor Terminals VBRG -5 55 V 3
Switched Bridge Terminal VBRS -0.3 55 V BRSW 3
Sense Amplifier Inputs VCSI -4 6.5 V CSP, CSM 3
Ambient Operating Temperature Range TA -40 150 °C 3
Maximum Continuous Junction Temperature TJ(max) 165 °C 3
Transient Junction Temperature TJt 180 °C Over temperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours, guaranteed by design characterization. 3
Storage Temperature Range Tstg -55 150 °C 3
VBB Functional Operating Range VBB 5.5 50 V Operating; outputs active 6
VBB Quiescent Current IBBQ 25 28 mA VBB = 12 V, all gate drive outputs low 6
VBB Sleep State Current IBBS 10 µA VLIN = VBB = 12 V, in sleep state 6
VREG Output Voltage (VRG=0) VREG 7.5 8 8.5 V VRG = 0, VBB ≥ 8.5 V, IVREG = 0 to 35 mA 6
VREG Output Voltage (VRG=1) VREG 9 11 11.7 V VRG = 1, VBB ≥ 9 V, IVREG = 0 to 33 mA 6
VLR Output Voltage (VLR=0) VLR 3.1 3.3 3.5 V VLR = 0, IVLR < 70 mA, VBB > 6 V 6
VLR Output Voltage (VLR=1) VLR 4.8 5 5.2 V VLR = 1, IVLR < 70 mA, VBB > 6.5 V 6
VLR Regulator Current Limit ILROC 130 300 mA 6
VLR Regulator Enable Voltage Threshold VLROE 1.5 V VLR rising 6
BRSW Switch Impedance RBRSW 50 250 Ω IBRSW = -5 mA 6
Bootstrap Diode Forward Voltage VfBOOT 1.5 2.2 2.8 V ID = 100 mA 6
Pull-Up On-Resistance (TJ=25°C) RDS(on)UP 5 8 11 Ω TJ = 25°C, IGH = -150 mA 7
Pull-Up On-Resistance (TJ=150°C) RDS(on)UP 10 15 20 Ω TJ = 150°C, IGH = -150 mA 7
Pull-Down On-Resistance (TJ=25°C) RDS(on)DN 1.5 2.4 3.1 Ω TJ = 25°C, IGL = 150 mA 7
Pull-Down On-Resistance (TJ=150°C) RDS(on)DN 2.9 4 5 Ω TJ = 150°C, IGL = 150 mA 7
Pull-Up Peak Source Current IPUPK -1500 -450 -200 mA VGS = 0 V 7
Pull-Down Peak Sink Current IPDPK 425 800 1330 mA VGS > 9 V 7
Turn-Off Propagation Delay tP(off) 60 90 140 ns Input change to unloaded gate output change; DT[5:0] = 0 7
Turn-On Propagation Delay tP(on) 50 80 130 ns Input change to unloaded gate output change; DT[5:0] = 0 7
Dead Time Default Power-Up Value tDEAD 1.52 1.6 1.68 µs Default power-up value 7
Dead Time Programmable Range tDEAD 0.1 3.15 µs Programmable range 7
System Clock Period tOSC 47.5 50 52.5 ns 6
Input Low Voltage (VIO=0) VIL 1.05 V All digital inputs except IG, VIO = 0 8
Input Low Voltage (VIO=1) VIL 1.56 V All digital inputs except IG, VIO = 1 8
Input High Voltage (VIO=0) VIH 2.17 V All digital inputs except IG, VIO = 0 8
Input High Voltage (VIO=1) VIH 3.36 V All digital inputs except IG, VIO = 1 8
Input Hysteresis VIhys 250 550 mV All digital inputs except IG 8
Output Low Voltage VOL 0.4 V SDO, MRSTn, BXM, LRX, IOL = 1 mA 8
Output Low Voltage DIAG VOLD 0.2 0.4 V DIAG, IOD = 3 mA, DIAG active 8
VBB Undervoltage Lockout (VBBON, VLR=0) VBBON 4.3 4.8 V VBB rising, VLR = 0 12
VBB POR Voltage VBBR 3.2 3.7 V VBB falling 12
VREG Undervoltage Rising (VRG=0) VRON 6.4 6.6 6.8 V VREG rising, VRG = 0 13
Watchdog Minimum Time Default tWM 0.95 1 1.05 ms Default power-up value 8
Watchdog Window Time Default tWW 9.5 10 10.5 ms Default power-up value 8
MRSTn Low tMRST 9.5 10 10.5 ms 8
ENABLE Input Timeout tETO 90 100 110 ms 13
Input Offset Voltage VIOS -2 2 mV 11
Output Voltage Clamp VCSC 4.8 5.2 5.6 V ICSO = -1 mA 11
Temperature Warning Threshold TJW 125 135 145 °C Temperature increasing 14
Overtemperature Threshold TJF 170 175 180 °C Temperature increasing 14
VDS Threshold Default Level VDST 1 1.2 1.4 V Default power-up level 13
Overcurrent Threshold Voltage Default VOCT 492 600 708 mV Default power-up value 13
Thermal Resistance, 4-layer PCB (JEDEC) RθJA 24 °C/W 4-layer PCB based on JEDEC standard 3
Thermal Resistance, 2-layer PCB 3.8 in² copper each side RθJA 44 °C/W 2-layer PCB with 3.8 in.2 of copper area each side 3
Thermal Resistance Junction-to-Pad RθJP 2 °C/W 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin QFN package (suffix EV). This package is lead (Pb) free with 100% matte-tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: AMT49105KEVTR-J
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: amt49105kevtr-j-etched.step / amt49105kevtr-j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amt49105kevtr-j.step / amt49105kevtr-j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (73 pp, sha256 8c36e089ba9b6cc3, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF