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AMT49100KJPTR-B-3

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Allegro MicroSystems, LLC Gate Drivers, LQFP-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsamt49100kjptr-b-3factory-2.0.0extractor-text

Verified AMT49100KJPTR-B-3

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier lcsc, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AMT49100KJPTR-B-3 · LQFP-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 73-page datasheet
  • ✓distributor: lcsc C19762009, digikey 620-AMT49100KJPTR-B-3-ND, mouser 250-AMT49100KJPTRB3
  • ✓family: LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-x8vtoig_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ amt49100kjptr-b-3.kicad_sym✓ amt49100kjptr-b-3.kicad_mod✓ amt49100kjptr-b-3.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 4d ago
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amt49100kjptr-b-3-hero.glb amt49100kjptr-b-3: hero GLB from the etched model (keeps the MPN mark) · Ray 4d ago
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verification.json Verified: Published by the parts factory: tier lcsc, 49 pins · Ray 4d ago

AMT49100KJPTR-B-3

Allegro MicroSystems, LLC · Gate Drivers · LQFP-48-EP(7x7)

AMT49100KJPTR-B-3 from Allegro MicroSystems, LLC, in a LQFP-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LA input Logic input controlling the phase A low-side gate drive, selectable active high or low with pull-down/pull-up, battery-voltage compliant (up to 80 V).
2 HB input Logic input controlling the phase B high-side gate drive, selectable active high or low with pull-down/pull-up, battery-voltage compliant (up to 80 V).
3 LB input Logic input controlling the phase B low-side gate drive, selectable active high or low with pull-down/pull-up, battery-voltage compliant (up to 80 V).
4 HC input Logic input controlling the phase C high-side gate drive, selectable active high or low with pull-down/pull-up, battery-voltage compliant (up to 80 V).
5 LC input Logic input controlling the phase C low-side gate drive, selectable active high or low with pull-down/pull-up, battery-voltage compliant (up to 80 V).
6 DIAG output Programmable diagnostic output providing fault flag (default), pulsed fault flag, temperature, or internal timer; rated -0.3 to 80 V.
7 SAL output Logic-level output showing the phase A state from a programmable threshold comparator.
8 SBL output Logic-level output showing the phase B state from a programmable threshold comparator.
9 SCL output Logic-level output showing the phase C state from a programmable threshold comparator.
10 SDO tri_state Serial data output, high impedance when STRn is high, outputs the status register fault flag (bit 15) as soon as STRn goes low.
11 SDI input Serial data logic input with pull-down, 16-bit word MSB first.
12 SCK input Serial clock logic input with pull-down, data latched on rising edge, 16 rising edges per write, must be held high when STRn changes.
13 STRn input Serial strobe (chip select) input with pull-up; when high, SCK and SDI activity is ignored and SDO is high impedance.
14 CS1P input Current sense amplifier 1 positive input, rated -4 to 6.5 V.
15 CS1M input Current sense amplifier 1 negative input, rated -4 to 6.5 V.
16 CS1O output Current sense amplifier 1 output, rated -0.3 to 6 V.
17 CS2P input Current sense amplifier 2 positive input, rated -4 to 6.5 V.
18 CS2M input Current sense amplifier 2 negative input, rated -4 to 6.5 V.
19 CS2O output Current sense amplifier 2 output, rated -0.3 to 6 V.
20 CS3P input Current sense amplifier 3 positive input, rated -4 to 6.5 V.
21 CS3M input Current sense amplifier 3 negative input, rated -4 to 6.5 V.
22 CS3O output Current sense amplifier 3 output, rated -0.3 to 6 V.
23 LSSC passive Low-side source return for phase C, connected to the low-side MOSFET source through a low-impedance track for gate discharge.
24 GLC output Low-side gate drive output for the phase C external N-channel MOSFET.
25 CC passive Phase C bootstrap capacitor high-side connection and positive supply for the high-side gate driver.
26 SC passive Phase C load connection sensing switched load voltage, negative side of the bootstrap capacitor and floating high-side driver supply return.
27 GHC output High-side gate drive output for the phase C external N-channel MOSFET.
28 LSSB passive Low-side source return for phase B, connected to the low-side MOSFET source through a low-impedance track for gate discharge.
29 GLB output Low-side gate drive output for the phase B external N-channel MOSFET.
30 CB passive Phase B bootstrap capacitor high-side connection and positive supply for the high-side gate driver.
31 SB passive Phase B load connection sensing switched load voltage, negative side of the bootstrap capacitor and floating high-side driver supply return.
32 GHB output High-side gate drive output for the phase B external N-channel MOSFET.
33 LSSA passive Low-side source return for phase A, connected to the low-side MOSFET source through a low-impedance track for gate discharge.
34 GLA output Low-side gate drive output for the phase A external N-channel MOSFET.
35 CA passive Phase A bootstrap capacitor high-side connection and positive supply for the high-side gate driver.
36 SA passive Phase A load connection sensing switched load voltage, negative side of the bootstrap capacitor and floating high-side driver supply return.
37 GHA output High-side gate drive output for the phase A external N-channel MOSFET.
38 VREG power_out Regulated gate drive supply, nominally 12 V, from the buck regulator or an external supply, requires at least 10 µF ceramic capacitor.
39 GND power_in Ground; both GND terminals must be connected together at the device.
40 GND power_in Ground; both GND terminals must be connected together at the device.
41 CP2 passive Charge pump capacitor terminal, connect at least 1 µF ceramic capacitor to CP1.
42 CP1 passive Charge pump capacitor terminal, connect at least 1 µF ceramic capacitor to CP2.
43 VBRG input Sense input to the top of the external MOSFET bridge and reference for the charge pump and NVM programming; needs at least 100 nF to GND, operating 4.5 to 80 V.
44 VBB power_in Main power supply of 10 to 80 V via reverse-voltage protection, decoupled with ceramic capacitors close to the pin.
45 HA input Logic input controlling the phase A high-side gate drive, selectable active high or low with pull-down/pull-up, battery-voltage compliant (up to 80 V).
46 ENABLE input Disables all gate drive outputs when pulled low in direct mode or after a timeout in watchdog mode; can be pulled to VBB.
47 RESETn input Resets faults when pulsed low and forces sleep when held low longer than tRSD; can be pulled to VBB.
48 LX output Buck converter inductor switching node, rated -1 to 80 V.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Allegro MicroSystems, LLC
Package LQFP-48-EP(7x7)
Category Motor Driver ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VBB -0.3 80 V 3
Drive Regulator Terminal VREG -0.3 16 V 3
Buck Switch Terminal VLX -1 80 V LX 3
Battery-Compliant Logic Input Terminals VIB -0.3 80 V HA, HB, HC, LA, LB, LC, ENABLE, RESETn 3
Logic Input Terminals VI -0.3 6 V STRn, SCK, SDI 3
Logic Output Terminals VO -0.3 6 V SDO, SAL, SBL, SCL 3
Diagnostic Output Terminal VDIAG -0.3 80 V DIAG 3
Sense Amplifier Inputs VCSI -4 6.5 V CSxP, CSxM 3
Sense Amplifier Output VCSO -0.3 6 V CSxO 3
Bridge Drain Monitor Terminal VBRG -5 85 V VBRG 3
Ambient Operating Temperature Range TA -40 150 °C Limited by power dissipation 3
Maximum Continuous Junction Temperature TJ(max) 165 °C 3
Transient Junction Temperature TJt 180 °C Over temperature event not exceeding 10 seconds, lifetime duration not exceeding 10 hours, guaranteed by design characterization. 3
Storage Temperature Range Tstg -55 150 °C 3
VBB Quiescent Current, Regulator Inactive IBBQ 1 2 mA VBB = VREG = 12 V, all gate drive outputs low 6
VBB Sleep Current IBBS 10 µA VRESETn ≤ 300 mV, sleep mode, VBB < 60 V 6
VBRG Operating Range VBRG 4.5 48 80 V 6
VBRG Input Current IBRGQ 3 5 mA 6
VBRG Sleep Input Current IBRGS 2 µA VRESETn ≤ 300 mV, sleep mode, VBRG < 60 V 6
VREG Functional Operating Input Range, Regulator Inactive VREG 11 14.5 V Operating; outputs active 6
VREG Quiescent Current, Regulator Inactive IREGQ 20 30 mA VREG = 12 V, all gate drive outputs low 6
VREG Sleep Current IREGS 100 µA VRESETn ≤ 300 mV, sleep mode, VREG = 12 V 6
Internal Logic I/O Regulator Voltage VIO 3.1 3.3 3.5 V VIO = 0, VREG > 6.5 V 6
Bootstrap Boost Voltage VCX 7.9 9.1 11 V w.r.t. VBRG, Boot capacitor fully charged 6
Bootstrap Diode Forward Voltage VfBOOT 0.4 0.7 1 V ID = 10 mA 6
Bootstrap Diode Current Limit IDBOOT 250 500 750 mA 6
System Clock Period tOSC 45 50 55 ns 6
Turn-On Time (High-Side) tr(HS) 110 454 ns CLOAD = 30 nF, 2 V to 8 V, VCx, VSx = 11 V 7
Turn-Off Time (High-Side) tf(HS) 47 250 ns CLOAD = 30 nF, 8 V to 2 V, VCx, VSx = 11 V 7
Pull-Up On-Resistance RDS(on)UP 2.5 8 Ω TJ = 25°C, IGH = -150 mA 7
Pull-Down On-Resistance RDS(on)DN 0.6 1.9 Ω TJ = 25°C, IGL = 150 mA 7
Number of Write Cycles NWC 400 TJ ≤ 85ºC 7
Turn-Off Propagation Delay tP(off) 73 ns Phase input change to unloaded gate output change (see Figure 4); DT[6:0] = 0 8
Turn-On Propagation Delay tP(on) 58 ns Phase input change to unloaded gate output change (see Figure 4); DT[6:0] = 0 8
Dead Time (Turn-Off to Turn-On Delay) tDEAD 1.35 1.6 1.85 µs Default power-up state (see Figure 4) 8
Input Low Voltage VIL 0.8 V RESETn 9
Input High Voltage VIH 2.4 V RESETn 9
Input Hysteresis VIhys 200 550 800 mV Except RESETn 9
Output Low Voltage VOL 0.2 0.4 V IOL = 1 mA 9
Output Leakage SDO IOSD -1 1 µA 0 V < VSDO < VIO, STRn = 1 9
Reset Pulse Width tRST 1 4.5 µs 9
Clock High Time tSCKH 50 ns A in Figure 3 9
Data In Setup Time To Clock Rising tSDIS 15 ns J in Figure 3 9
Input Offset Voltage VIOS -1 1 mV After VIOS calibration 10
Gain Error EA -1.6 1.6 % VCM in range 10
Gain Drift Over Temperature EAD -50 50 ppm/°C VCM in range 10
Input Common-Mode Range (DC) VCM -1.5 2 V VID = 0 V 10
Small Signal -3 dB Bandwidth BW 1 MHz Gain = 20 V/V, VIN = 10 mVpp 10
VREG Undervoltage Rising VRON 7.7 8 8.3 V VREG rising 11
VREG Undervoltage Falling VROFF 7 7.25 7.5 V VREG falling 11
VREG Overvoltage Warning VROV 14.8 15.4 16.1 V VREG rising 11
VBB Undervoltage Rising VBBON 9.1 9.5 9.9 V VBB rising 11
VBB Undervoltage Falling VBBOFF 8.1 8.5 8.9 V VBB falling 11
ENABLE Input Timeout tETO 90 100 110 ms 11
Temperature Warning Threshold TJW 125 135 145 °C Temperature increasing 12
Overtemperature Threshold TJF 165 175 185 °C Temperature increasing 12
Thermal Resistance Junction-to-Ambient, JP Package RθJA 23 °C/W 4-layer PCB based on JEDEC standard 3
Thermal Resistance Junction-to-Ambient, JP Package RθJA 44 °C/W 2-layer PCB with 3.8 in.2 of copper area each side 3
Thermal Resistance Junction-to-Pad, JP Package RθJP 2 °C/W 3

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin with exposed thermal pad. The package is lead (Pb) free with 100% matte-tin leadframe plating. 1

CAD (KiCad official)

  • Symbol: AMT49100KJPTR-B-3
  • Footprint: Package_QFP:LQFP-48-1EP_7x7mm_P0.5mm_EP3.6x3.6mm
  • 3D model: LQFP-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: amt49100kjptr-b-3-etched.step / amt49100kjptr-b-3-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amt49100kjptr-b-3.step / amt49100kjptr-b-3.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Allegro MicroSystems, LLC datasheet (73 pp, sha256 b8b11ad0be155771, retrieved 2026-10-31, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF