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AMIS30660CANH2RG

Public Made by Adom

by adom

onsemi CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AMIS30660CANH2RG

onsemi · CAN ICs · SOIC-8

AMIS30660CANH2RG from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TxD input Transmit data input; low input drives the bus dominant, with an internal pull-up current (pulled high internally if disconnected); VIH min 2.0 V, VIL max 0.8 V.
2 GND power_in Ground reference for all voltages.
3 VCC power_in Supply voltage, 4.75 V to 5.25 V operating, absolute maximum 7 V.
4 RxD output Receive data output; dominant transmitter gives a low output, with VOL max 0.45 V at 6 mA.
5 VREF power_in Reference voltage output, nominally 0.50 x VCC (0.45 to 0.55 x VCC for -50 uA to +50 uA load).
6 CANL bidirectional Low-level CAN bus line (low in dominant mode), rated -45 V to +45 V DC and protected against automotive transients.
7 CANH bidirectional High-level CAN bus line (high in dominant mode), rated -45 V to +45 V DC and protected against automotive transients.
8 S input Silent mode control input with internal pull-down current; low or floating selects high-speed mode, high (VCC) selects silent mode with the transmitter disabled.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-8
Category Interface ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (abs max) VCC -0.3 7 V 3
DC voltage at CANH (abs max) VCANH -45 45 V 0 < VCC < 5.25 V; No Time Limit 3
DC voltage at CANL (abs max) VCANL -45 45 V 0 < VCC < 5.25 V; No Time Limit 3
Transient voltage at CANH Vtran(CANH) -150 150 V Note 2 (ISO 7637 pulses) 3
Transient voltage at CANL Vtran(CANL) -150 150 V Note 2 (ISO 7637 pulses) 3
ESD voltage, human body model Vesd -4 4 kV All pins; Note 3 3
ESD voltage, charged device model Vesd -500 500 V All pins; Note 5 3
Static latchup Latchup 100 mA All pins; Note 4 3
Storage temperature Tstg -55 155 °C 3
Ambient temperature Tamb -40 125 °C 3
Junction temperature TJunc -40 150 °C 3
Thermal resistance junction-to-ambient Rth(vj-a) 150 K/W SOIC-8, In Free Air 3
Thermal resistance junction-to-substrate Rth(vj-s) 45 K/W Bare die, In Free Air 3
Supply current, dominant ICC 25 45 65 mA Dominant; VTXD = 0 V 5
Supply current, recessive ICC 2 4 8 mA Recessive; VTXD = VCC 5
Supply current in silent mode ICCS 2 4 8 mA VS = VCC 5
TxD high-level input voltage VIH 2 V Output recessive 5
TxD low-level input voltage VIL -0.3 0.8 V Output dominant 5
TxD high-level input current IIH -1 0 1 µA VTxD = VCC 5
TxD low-level input current IIL -75 -200 -350 µA VTxD = 0 V 5
TxD input capacitance Ci 5 10 pF Not tested 5
S high-level input voltage VIH 2 V Silent mode 5
S low-level input voltage VIL -0.3 0.8 V High-speed mode 5
S high-level input current IIH 20 30 50 µA VS = 2 V 5
S low-level input current IIL 15 30 45 µA VS = 0.8 V 5
RxD high-level output voltage (multiple of VCC) VOH 0.6 0.75 V IRXD = -10 mA; printed 0.6 x VCC min, 0.75 x VCC typ 5
RxD low-level output voltage VOL 0.25 0.45 V IRXD = 6 mA 5
Reference output voltage (multiple of VCC) VREF 0.45 0.5 0.55 V -50 µA < IVREF < +50 µA; printed as x VCC 5
Reference output voltage for full common mode range (multiple of VCC) VREF_CM 0.4 0.5 0.6 V -35 V < VCANH < +35 V; -35 V < VCANL < +35 V; printed as x VCC 5
Recessive bus voltage at CANH Vo(reces)(CANH) 2 2.5 3 V VTxD = VCC; no load 5
Recessive bus voltage at CANL Vo(reces)(CANL) 2 2.5 3 V VTxD = VCC; no load 5
Recessive output current at CANH Io(reces)(CANH) -2.5 2.5 mA -35 V < VCANH < +35 V; 0 V < VCC < 5.25 V 5
Recessive output current at CANL Io(reces)(CANL) -2.5 2.5 mA -35 V < VCANL < +35 V; 0 V < VCC < 5.25 V 5
Dominant output voltage at CANH Vo(dom)(CANH) 3 3.6 4.25 V VTxD = 0 V 5
Dominant output voltage at CANL Vo(dom)(CANL) 0.5 1.4 1.75 V VTxD = 0 V 5
Differential bus output voltage, dominant Vo(dif)(bus) 1.5 2.25 3 V VTxD = 0 V; dominant; 42.5 Ω < RLT < 60 Ω 5
Differential bus output voltage, recessive Vo(dif)(bus) -120 0 50 mV VTxD = VCC; recessive; No load 5
Short circuit output current at CANH Io(sc)(CANH) -45 -70 -95 mA VCANH = 0 V; VTxD = 0 V 5
Short circuit output current at CANL Io(sc)(CANL) 45 70 120 mA VCANL = 36 V; VTxD = 0 V 5
Differential receiver threshold voltage Vi(dif)(th) 0.5 0.7 0.9 V -5 V < VCANL < +10 V; -5 V < VCANH < +10 V; See Figure 4 6
Differential receiver threshold voltage for high common-mode Vihcm(dif)(th) 0.25 0.7 1.05 V -35 V < VCANL < +35 V; -35 V < VCANH < +35 V; See Figure 4 6
Differential receiver input voltage hysteresis Vi(dif)(hys) 50 70 100 mV -5 V < VCANL < +10 V; -5 V < VCANH < +10 V; See Figure 4 6
Common-mode input resistance at CANH Ri(cm)(CANH) 15 25 37 kΩ 6
Common-mode input resistance at CANL Ri(cm)(CANL) 15 25 37 kΩ 6
Matching of common-mode input resistance Ri(cm)(m) -3 0 3 % VCANH = VCANL 6
Differential input resistance Ri(dif) 25 50 75 kΩ 6
Input capacitance at CANH Ci(CANH) 7.5 20 pF VTxD = VCC; not tested 6
Input capacitance at CANL Ci(CANL) 7.5 20 pF VTxD = VCC; not tested 6
Differential input capacitance Ci(dif) 3.75 10 pF VTxD = VCC; not tested 6
Input leakage current at CANH ILI(CANH) 10 170 250 µA VCC = 0 V; VCANH = 5 V 6
Input leakage current at CANL ILI(CANL) 10 170 250 µA VCC = 0 V; VCANL = 5 V 6
Common-mode peak VCM-peak -500 500 mV See Figures 7 and 8 6
Common-mode step VCM-step -150 150 mV See Figures 7 and 8 6
POR level PORL 2.2 3.5 4.5 V CANH, CANL, Vref in tri-state below POR level 6
Shutdown junction temperature Tj(sd) 150 160 180 °C 6
Delay TxD to bus active td(TxD-BUSon) 40 85 130 ns Vs = 0 V 6
Delay TxD to bus inactive td(TxD-BUSoff) 30 60 105 ns Vs = 0 V 6
Delay bus active to RxD td(BUSon-RxD) 25 55 105 ns Vs = 0 V 6
Delay bus inactive to RxD td(BUSoff-RxD) 65 100 135 ns Vs = 0 V 6
Propagation delay TxD to RxD, recessive to dominant tpd(rec-dom) 70 245 ns Vs = 0 V 6
Propagation delay TxD to RxD, dominant to recessive td(dom-rec) 100 245 ns Vs = 0 V 6
TxD dominant time for time out tdom(TxD) 250 450 750 µs VTxD = 0 V 6

CAD (KiCad official)

  • Symbol: AMIS30660CANH2RG
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: amis30660canh2rg-etched.step / amis30660canh2rg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amis30660canh2rg.step / amis30660canh2rg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (10 pp, sha256 894b252bf7163a0c, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF