main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5h ago
viewers amc7823irtar: viewers · Ray 5h ago
amc7823irtar-etched.glb Publish 0.1.0 · Ray 5h ago
amc7823irtar-etched.step amc7823irtar: factory component page (tier=mfr) · Ray 5h ago
amc7823irtar-hero.glb amc7823irtar: hero GLB from the etched model (keeps the MPN mark) · Ray 5h ago
amc7823irtar-hero.overlay.json Publish 0.1.0 · Ray 5h ago
amc7823irtar.glb Publish 0.1.0 · Ray 5h ago
amc7823irtar.kicad_mod Publish 0.1.0 · Ray 5h ago
amc7823irtar.kicad_sym Publish 0.1.0 · Ray 5h ago
amc7823irtar.lbr Publish 0.1.0 · Ray 5h ago
amc7823irtar.step Publish 0.1.0 · Ray 5h ago
package.json Publish 0.1.0 · Ray 5h ago
page.json Set visibility: public · Ray 5h ago
README.md Publish 0.1.0 · Ray 5h ago
verification.json Verified: Published by the parts factory: tier mfr, 41 pins · Ray 5h ago

AMC7823IRTAR

Texas Instruments · ADCs/DACs - Special Purpose · WQFN-40(6x6)

AMC7823IRTAR from Texas Instruments, in a WQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GALR output Global analog input out-of-range alarm; this pin goes low (active) when one or more of the first four accessed analog inputs is out of preset range.
2 DAV output Data available indicator; in auto-mode a 2μs active-low pulse appears on this pin when a conversion cycle finishes, and it stays high when deactivated.
3 ELDAC input External DAC synchronous load trigger; DACs selected for external synchronous load update simultaneously on the rising edge of ELDAC.
4 ISET_RESISTOR passive The resistor connected from the analog supply to this pin sets the current output from PRECISION_I_OUTPUT; the voltage across the set resistor should be limited to about 0.5V.
5 PRECISION_I_OUTPUT output Current output to drive a thermistor, with output current range 0.01 mA to 10 mA and compliance voltage of about 2V.
6 DAC 0_OUT output Output of DAC 0, programmable from 0 to VREF or 0 to 2 × VREF.
7 DAC 1_OUT output Output of DAC 1, programmable from 0 to VREF or 0 to 2 × VREF.
8 DAC 2_OUT output Output of DAC 2, programmable from 0 to VREF or 0 to 2 × VREF.
9 DAC 3_OUT output Output of DAC 3, programmable from 0 to VREF or 0 to 2 × VREF.
10 SGND power_in Analog input signal ground; must connect to the ground of the analog input source to minimize digital noise.
11 CH0 passive Analog input channel 0, with input range 0 to 2 × VREF.
12 CH1 passive Analog input channel 1, with input range 0 to 2 × VREF.
13 CH2 passive Analog input channel 2, with input range 0 to 2 × VREF.
14 CH3 passive Analog input channel 3, with input range 0 to 2 × VREF.
15 AGND power_in Analog ground.
16 AVDD power_in Analog power supply, +3V to +5V; must be the same value as DVDD.
17 CH4 passive Analog input channel 4, with input range 0 to 2 × VREF.
18 CH5 passive Analog input channel 5, with input range 0 to 2 × VREF.
19 CH6 passive Analog input channel 6, with input range 0 to 2 × VREF.
20 CH7 passive Analog input channel 7, with input range 0 to 2 × VREF.
21 EXT_REF_IN bidirectional External reference input; when internal reference is selected it works as the internal reference output with 10kΩ output impedance.
22 DAC 4_OUT output Output of DAC 4, programmable from 0 to VREF or 0 to 2 × VREF.
23 DAC 5_OUT output Output of DAC 5, programmable from 0 to VREF or 0 to 2 × VREF.
24 DAC 6_OUT output Output of DAC 6, programmable from 0 to VREF or 0 to 2 × VREF.
25 DAC 7_OUT output Output of DAC 7, programmable from 0 to VREF or 0 to 2 × VREF.
26 RESET input Reset input; a logic low on this pin causes the part to perform a hardware reset.
27 GPIO-0/ALR0 bidirectional Multiple-function I/O pin that works as digital I/O or as the ALR pin of the first analog input; an external pull-up is required when used as output.
28 GPIO-1/ALR1 bidirectional Multiple-function I/O pin that works as digital I/O or as the ALR pin of the second analog input; an external pull-up is required when used as output.
29 GPIO-2/ALR2 bidirectional Multiple-function I/O pin that works as digital I/O or as the ALR pin of the third analog input; an external pull-up is required when used as output.
30 GPIO-3/ALR3 bidirectional Multiple-function I/O pin that works as digital I/O or as the ALR pin of the fourth analog input; an external pull-up is required when used as output.
31 CONVERT input External conversion trigger; the rising edge starts ADC sampling and conversion when external trigger mode is selected.
32 SCLK input Serial clock input for the SPI interface.
33 MOSI input Master out, slave in; digital data input for the serial interface.
34 MISO output Master in, slave out; digital data output for the serial interface, high impedance when SS is high.
35 SS input Active-low slave select input; data is not clocked into MOSI unless SS is low.
36 BVDD power_in Interface power supply; connect to 3V for 3V logic or 5V for 5V logic, and it must not exceed AVDD or DVDD.
37 DVDD power_in Digital power supply, +3V to +5V; must be the same value as AVDD.
38 DGND power_in Digital ground.
39 GPIO-4 bidirectional Dedicated general-purpose bidirectional digital I/O pin.
40 GPIO-5 bidirectional Dedicated general-purpose bidirectional digital I/O pin.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40(6x6)
Category Data Acquisition
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage to GND AVDD, DVDD, BVDD -0.3 6 V Over operating free-air temperature range 2
Digital input voltage to GND -0.3 V max BVDD + 0.3 V 2
Analog input voltage to GND -0.3 V max AVDD + 0.3 V 2
Input current, continuous -20 20 mA 2
Input current, momentary -100 100 mA 2
Operating temperature range -40 105 °C 2
Storage temperature range -65 150 °C 2
Junction temperature range (TJ max) TJ 150 °C 2
Thermal impedance junction-to-case θJC 15 °C/W 2
Thermal impedance junction-to-ambient θJA 60 °C/W 2
ADC integral linearity -1.25 1.25 LSB +5V electrical characteristics 3
ADC differential linearity -1 1.25 LSB +5V electrical characteristics 3
ADC offset error -2 2 LSB +5V electrical characteristics 3
ADC offset error drift -4 4 ppmFS/°C +5V electrical characteristics 3
ADC gain error -6 6 LSB +5V electrical characteristics 3
ADC gain error match 0.3 1 LSB +5V electrical characteristics 3
DAC output current -1 1 mA Refer to Typical Characteristics 3
DAC integral linearity 2 8 LSB Measured from code 0x008 to 0xFFF 3
DAC differential linearity 0.2 1 LSB +5V electrical characteristics 3
DAC offset error 0.5 5 mV Output range = 0 to VREF 3
DAC offset error 1 10 mV Output range = 0 to 2 × VREF 3
DAC offset error drift -4 4 ppmFS/°C +5V electrical characteristics 3
DAC gain error 0.3 1 %FS Output range = 0 to 2 × VREF 3
Precision current source output current range 0.01 10 mA 4
Output current accuracy 99.5 100 100.5 μA Iout = 100μA 4
Output current drift 40 ppm/°C Iout = 100μA 4
Compliance voltage of pin 3 4.25 V Iout = 10mA 4
Internal reference voltage 2.495 2.5 2.505 V At +25°C 4
Internal reference drift -15 15 ppm/°C -40°C to +85°C 4
Short-circuit current 250 μA 4
External reference voltage 1.2 2.55 V 4
Temperature sensor accuracy -4 4 °C VREF = 2.5V 4
Temperature sensor accuracy -2 2 °C VREF = 1.25V 4
Level of pin GALR and DAV, high output VOH 2.4 V IOH = 0.7mA; max BVDD 4
Level of pin GALR and DAV, low output VOL 0 0.4 V IOL = 180μA 4
Digital input high level (BVDD = 5V) VIH 3.5 V BVDD = 5V, IIH = 5μA; max BVDD + 0.3 V 4
Digital input low level (BVDD = 5V) VIL 0 0.8 V BVDD = 5V, IIL = -5μA 4
Digital output high level (BVDD = 5V) VOH 4 V BVDD = 5V, IOH = -3mA 4
Digital output low level (BVDD = 5V) VOL 0 0.4 V BVDD = 5V, IOL = 3mA 4
Digital input high level (BVDD = 3V) VIH 2.1 V BVDD = 3V, IIH = 5μA; max BVDD + 0.3 V 4
Digital input low level (BVDD = 3V) VIL 0 0.6 V BVDD = 3V, IIL = -5μA 4
Digital output high level (BVDD = 3V) VOH 2.4 V BVDD = 3V, IOH = -3mA 4
Digital output low level (BVDD = 3V) VOL 0 0.4 V BVDD = 3V, IOL = 3mA 4
Power-supply voltage AVDD AVDD 2.7 5 5.5 V +5V electrical characteristics 5
Power-supply voltage DVDD DVDD 2.7 5.5 V +5V electrical characteristics 5
Power-supply voltage BVDD BVDD 2.7 5.5 V +5V electrical characteristics 5
Quiescent current of AVDD in normal operation IDD 15 20 mA In normal operation, precision current source = 0, no DAC load 5
Specified performance temperature range -40 85 °C 5
ADC offset error -3 3 LSB +3V electrical characteristics 6
ADC gain error -12 12 LSB +3V electrical characteristics 6
ADC gain error match 0.3 1.5 LSB +3V electrical characteristics 6
DAC gain error 0.2 1 %FS Output range = 0 to 2 x VREF, +3V 6
Compliance voltage of pin 1.9 2 V AVDD = 2.7V, Iout = 10mA 7
Internal reference voltage 1.247 1.25 1.253 V At +25°C, +3V electrical characteristics 7
Internal reference drift -20 20 ppm/°C -40°C to +85°C 7
Short-circuit current 125 μA +3V electrical characteristics 7
External reference voltage 1.2 1.28 V +3V electrical characteristics 7
Power-supply voltage AVDD AVDD 2.7 3 3.3 V +3V electrical characteristics 7
Quiescent current of AVDD in normal operation IDD 10 15 mA In normal operation, +3V electrical characteristics 7

CAD (KiCad official)

  • Symbol: AMC7823IRTAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: amc7823irtar-etched.step / amc7823irtar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amc7823irtar.step / amc7823irtar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 4ca9ccf47d69e7ab, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF