component
AMC23C12QDWVRQ1
Public Made by Adomby adom
Texas Instruments Isolated Comparators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AMC23C12QDWVRQ1
Texas Instruments · Isolated Comparators · SOIC-8
AMC23C12QDWVRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | High-side power supply, specified from 3 V to 25 V in the features list; see the Layout section for decoupling recommendations. |
| 2 | IN | input | Common analog input for window comparators 1 and 2; the comparator trips when the absolute value of this input exceeds the trip threshold. |
| 3 | REF | input | Reference pin that sets the trip threshold through a resistor to GND1, with an internal 100-μA current source and a filter capacitor to GND1; it can also be driven by an external voltage source. |
| 4 | GND1 | power_in | High-side ground for the input and threshold circuitry. |
| 5 | GND2 | power_in | Low-side ground for the output and low-side supply. |
| 6 | OUT1 | output | Open-drain output of window comparator 1; connect to an external pullup resistor or leave floating when not used. |
| 7 | OUT2 | output | Open-drain output of window comparator 2; connect to an external pullup resistor or leave floating when not used. |
| 8 | VDD2 | power_in | Low-side power supply, specified from 2.7 V to 5.5 V in the features list; see the Layout section for decoupling recommendations. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side supply voltage | VDD1 to GND1 | -0.3 | 30 | V | VDD1 to GND1 | 4 | |
| Low-side supply voltage | VDD2 to GND2 | -0.3 | 6.5 | V | VDD2 to GND2 | 4 | |
| REF analog input voltage | REF to GND1 | -0.5 | 6.5 | V | REF to GND1 | 4 | |
| IN analog input voltage | IN to GND1 | -6 | 5.5 | V | IN to GND1 | 4 | |
| Input current | -10 | 10 | mA | Continuous, any pin except power-supply pins | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -2000 | 2000 | V | Human-body model (HBM), per AEC Q100-002 | 4 | |
| ESD CDM | V(ESD) | -1000 | 1000 | V | Charged-device model (CDM), per AEC Q100-011 | 4 | |
| High-side power-supply voltage | VVDD1 | 3 | 5 | 25 | V | VDD1 to GND1 | 5 |
| Low-side power-supply voltage | VVDD2 | 2.7 | 3.3 | 5.5 | V | VDD2 to GND2 | 5 |
| Input voltage | VIN | -0.4 | 4 | V | IN to GND1, VDD1 > 4.3 V | 5 | |
| Reference voltage, window comparator mode | VREF | 20 | 300 | mV | REF to GND1 | 5 | |
| Reference voltage, positive-comparator mode, low hysteresis | VREF | 20 | 450 | mV | Low hysteresis mode | 5 | |
| Reference voltage, positive-comparator mode, high hysteresis | VREF | 600 | 2700 | mV | High hysteresis mode (Cmp0 only) | 5 | |
| Reference voltage headroom | VDD1, VREF | 1.4 | V | 5 | |||
| Filter capacitance on REF pin | 20 | 100 | nF | 5 | |||
| Sink current OUT | 0 | 4 | mA | 5 | |||
| Specified ambient temperature | TA | -40 | 25 | 125 | °C | 5 | |
| Junction-to-ambient thermal resistance | RθJA | 102.8 | °C/W | DWV (SOIC), 8 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 45.1 | °C/W | DWV (SOIC), 8 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 63 | °C/W | DWV (SOIC), 8 pins | 5 | ||
| Input resistance | RIN | 1 | GΩ | IN pin, 0 ≤ VIN ≤ 4 V | 8 | ||
| Input bias current | IBIAS | 0.1 | 25 | nA | IN pin, 0 ≤ VIN ≤ 4 V | 8 | |
| Input bias current | IBIAS | -310 | -0.5 | nA | IN pin, -400 mV ≤ VIN ≤ 0 V | 8 | |
| Input capacitance IN | CIN | 4 | pF | IN pin | 8 | ||
| Reference current | IREF | 99 | 100 | 101 | μA | REF to GND1, 20 mV < VREF ≤ 2.7 V | 8 |
| Mode selection threshold, rising | VMSEL | 500 | 550 | 600 | mV | VREF rising | 8 |
| Mode selection threshold, falling | VMSEL | 450 | 500 | 550 | mV | VREF falling | 8 |
| Mode selection threshold hysteresis | 50 | mV | 8 | ||||
| Cmp0 positive-going trip threshold error | EIT+ | -2 | 2 | mV | Cmp0, (VIT+, VREF, VHYS), VREF = 20 mV, VHYS = 4 mV | 8 | |
| Cmp0 positive-going trip threshold error | EIT+ | -5 | 5 | mV | Cmp0, (VIT+, VREF, VHYS), VREF = 2 V, VHYS = 25 mV | 8 | |
| Cmp0 negative-going trip threshold error | EIT- | -2.5 | 2.5 | mV | Cmp0, (VIT-, VREF), VREF = 20 mV | 8 | |
| Cmp0 negative-going trip threshold error | EIT- | -5 | 5 | mV | Cmp0, (VIT-, VREF), VREF = 2 V | 8 | |
| Cmp1 negative-going trip threshold error | EIT- | -3 | 3 | mV | Cmp1, (VIT- + VREF + VHYS), VREF = 20 mV, VHYS = 4 mV | 8 | |
| Cmp1 positive-going trip threshold error | EIT+ | -3.5 | 3.5 | mV | Cmp1, (VIT+ + VREF), VREF = 20 mV | 8 | |
| Trip threshold hysteresis | VHYS | 4 | mV | Cmp0 and Cmp1, (VIT+, VIT-), VREF ≤ 450 mV | 8 | ||
| Trip threshold hysteresis | VHYS | 25 | mV | Cmp0 only, (VIT+, VIT-), VREF ≥ 600 mV | 8 | ||
| Input capacitance LATCH | CIN | 4 | pF | LATCH pin | 8 | ||
| Low-level output voltage | VOL | 80 | 250 | mV | ISINK = 4 mA | 8 | |
| Open-drain output leakage current | ILKG | 5 | 100 | nA | VDD2 = 5 V, VOUT = 5 V | 8 | |
| Common-mode transient immunity | CMTI | 55 | 110 | V/ns | /VIN, VREF/ ≥ 4 mV, RPULLUP = 10 kΩ | 8 | |
| VDD1 undervoltage detection threshold, rising | VDD1UV | 3 | V | VDD1 rising | 9 | ||
| VDD1 undervoltage detection threshold, falling | VDD1UV | 2.9 | V | VDD1 falling | 9 | ||
| VDD1 power-on reset threshold | VDD1POR | 2.3 | V | VDD1 falling | 9 | ||
| VDD2 undervoltage detection threshold, rising | VDD2UV | 2.7 | V | VDD2 rising | 9 | ||
| VDD2 undervoltage detection threshold, falling | VDD2UV | 2.1 | V | VDD2 falling | 9 | ||
| High-side supply current | IDD1 | 3.2 | 4.3 | mA | 9 | ||
| Low-side supply current | IDD2 | 1.8 | 2.2 | mA | 9 | ||
| LATCH deglitch time | 1.8 | 3.2 | µs | Falling edge | 10 | ||
| Propagation delay time, /VIN/ rising | tpH | 280 | 410 | ns | VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF | 10 | |
| Propagation delay time, /VIN/ rising | tpH | 240 | 370 | ns | VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF | 10 | |
| Propagation delay time, /VIN/ falling | tpL | 280 | 410 | ns | VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF | 10 | |
| Propagation delay time, /VIN/ falling | tpL | 240 | 370 | ns | VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF | 10 | |
| Output signal fall time | tf | 2 | ns | RPULLUP = 4.7 kΩ, CL = 15 pF | 10 |
CAD (KiCad official)
- Symbol:
AMC23C12QDWVRQ1 - Footprint:
Package_SO:SOIC-8_7.5x5.85mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
amc23c12qdwvrq1-etched.step/amc23c12qdwvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);amc23c12qdwvrq1.step/amc23c12qdwvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (43 pp, sha256
f2ed3aa900354fc3, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AMC23C12QDWVRQ1
**Texas Instruments** · Isolated Comparators · SOIC-8
AMC23C12QDWVRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | High-side power supply, specified from 3 V to 25 V in the features list; see the Layout section for decoupling recommendations. |
| 2 | IN | input | Common analog input for window comparators 1 and 2; the comparator trips when the absolute value of this input exceeds the trip threshold. |
| 3 | REF | input | Reference pin that sets the trip threshold through a resistor to GND1, with an internal 100-μA current source and a filter capacitor to GND1; it can also be driven by an external voltage source. |
| 4 | GND1 | power_in | High-side ground for the input and threshold circuitry. |
| 5 | GND2 | power_in | Low-side ground for the output and low-side supply. |
| 6 | OUT1 | output | Open-drain output of window comparator 1; connect to an external pullup resistor or leave floating when not used. |
| 7 | OUT2 | output | Open-drain output of window comparator 2; connect to an external pullup resistor or leave floating when not used. |
| 8 | VDD2 | power_in | Low-side power supply, specified from 2.7 V to 5.5 V in the features list; see the Layout section for decoupling recommendations. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Signal Isolation Devices |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| High-side supply voltage | VDD1 to GND1 | -0.3 | | 30 | V | VDD1 to GND1 | 4 |
| Low-side supply voltage | VDD2 to GND2 | -0.3 | | 6.5 | V | VDD2 to GND2 | 4 |
| REF analog input voltage | REF to GND1 | -0.5 | | 6.5 | V | REF to GND1 | 4 |
| IN analog input voltage | IN to GND1 | -6 | | 5.5 | V | IN to GND1 | 4 |
| Input current | | -10 | | 10 | mA | Continuous, any pin except power-supply pins | 4 |
| Junction temperature | TJ | | | 150 | °C | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| ESD HBM | V(ESD) | -2000 | | 2000 | V | Human-body model (HBM), per AEC Q100-002 | 4 |
| ESD CDM | V(ESD) | -1000 | | 1000 | V | Charged-device model (CDM), per AEC Q100-011 | 4 |
| High-side power-supply voltage | VVDD1 | 3 | 5 | 25 | V | VDD1 to GND1 | 5 |
| Low-side power-supply voltage | VVDD2 | 2.7 | 3.3 | 5.5 | V | VDD2 to GND2 | 5 |
| Input voltage | VIN | -0.4 | | 4 | V | IN to GND1, VDD1 > 4.3 V | 5 |
| Reference voltage, window comparator mode | VREF | 20 | | 300 | mV | REF to GND1 | 5 |
| Reference voltage, positive-comparator mode, low hysteresis | VREF | 20 | | 450 | mV | Low hysteresis mode | 5 |
| Reference voltage, positive-comparator mode, high hysteresis | VREF | 600 | | 2700 | mV | High hysteresis mode (Cmp0 only) | 5 |
| Reference voltage headroom | VDD1, VREF | 1.4 | | | V | | 5 |
| Filter capacitance on REF pin | | 20 | | 100 | nF | | 5 |
| Sink current OUT | | 0 | | 4 | mA | | 5 |
| Specified ambient temperature | TA | -40 | 25 | 125 | °C | | 5 |
| Junction-to-ambient thermal resistance | RθJA | | 102.8 | | °C/W | DWV (SOIC), 8 pins | 5 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 45.1 | | °C/W | DWV (SOIC), 8 pins | 5 |
| Junction-to-board thermal resistance | RθJB | | 63 | | °C/W | DWV (SOIC), 8 pins | 5 |
| Input resistance | RIN | | 1 | | GΩ | IN pin, 0 ≤ VIN ≤ 4 V | 8 |
| Input bias current | IBIAS | | 0.1 | 25 | nA | IN pin, 0 ≤ VIN ≤ 4 V | 8 |
| Input bias current | IBIAS | -310 | -0.5 | | nA | IN pin, -400 mV ≤ VIN ≤ 0 V | 8 |
| Input capacitance IN | CIN | | 4 | | pF | IN pin | 8 |
| Reference current | IREF | 99 | 100 | 101 | μA | REF to GND1, 20 mV < VREF ≤ 2.7 V | 8 |
| Mode selection threshold, rising | VMSEL | 500 | 550 | 600 | mV | VREF rising | 8 |
| Mode selection threshold, falling | VMSEL | 450 | 500 | 550 | mV | VREF falling | 8 |
| Mode selection threshold hysteresis | | | 50 | | mV | | 8 |
| Cmp0 positive-going trip threshold error | EIT+ | -2 | | 2 | mV | Cmp0, (VIT+, VREF, VHYS), VREF = 20 mV, VHYS = 4 mV | 8 |
| Cmp0 positive-going trip threshold error | EIT+ | -5 | | 5 | mV | Cmp0, (VIT+, VREF, VHYS), VREF = 2 V, VHYS = 25 mV | 8 |
| Cmp0 negative-going trip threshold error | EIT- | -2.5 | | 2.5 | mV | Cmp0, (VIT-, VREF), VREF = 20 mV | 8 |
| Cmp0 negative-going trip threshold error | EIT- | -5 | | 5 | mV | Cmp0, (VIT-, VREF), VREF = 2 V | 8 |
| Cmp1 negative-going trip threshold error | EIT- | -3 | | 3 | mV | Cmp1, (VIT- + VREF + VHYS), VREF = 20 mV, VHYS = 4 mV | 8 |
| Cmp1 positive-going trip threshold error | EIT+ | -3.5 | | 3.5 | mV | Cmp1, (VIT+ + VREF), VREF = 20 mV | 8 |
| Trip threshold hysteresis | VHYS | | 4 | | mV | Cmp0 and Cmp1, (VIT+, VIT-), VREF ≤ 450 mV | 8 |
| Trip threshold hysteresis | VHYS | | 25 | | mV | Cmp0 only, (VIT+, VIT-), VREF ≥ 600 mV | 8 |
| Input capacitance LATCH | CIN | | 4 | | pF | LATCH pin | 8 |
| Low-level output voltage | VOL | | 80 | 250 | mV | ISINK = 4 mA | 8 |
| Open-drain output leakage current | ILKG | | 5 | 100 | nA | VDD2 = 5 V, VOUT = 5 V | 8 |
| Common-mode transient immunity | CMTI | 55 | 110 | | V/ns | /VIN, VREF/ ≥ 4 mV, RPULLUP = 10 kΩ | 8 |
| VDD1 undervoltage detection threshold, rising | VDD1UV | | 3 | | V | VDD1 rising | 9 |
| VDD1 undervoltage detection threshold, falling | VDD1UV | | 2.9 | | V | VDD1 falling | 9 |
| VDD1 power-on reset threshold | VDD1POR | | 2.3 | | V | VDD1 falling | 9 |
| VDD2 undervoltage detection threshold, rising | VDD2UV | | 2.7 | | V | VDD2 rising | 9 |
| VDD2 undervoltage detection threshold, falling | VDD2UV | | 2.1 | | V | VDD2 falling | 9 |
| High-side supply current | IDD1 | | 3.2 | 4.3 | mA | | 9 |
| Low-side supply current | IDD2 | | 1.8 | 2.2 | mA | | 9 |
| LATCH deglitch time | | | 1.8 | 3.2 | µs | Falling edge | 10 |
| Propagation delay time, /VIN/ rising | tpH | | 280 | 410 | ns | VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF | 10 |
| Propagation delay time, /VIN/ rising | tpH | | 240 | 370 | ns | VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF | 10 |
| Propagation delay time, /VIN/ falling | tpL | | 280 | 410 | ns | VDD2 = 3.3 V, VREF = 250 mV, VOVERDRIVE = 10 mV, CL = 15 pF | 10 |
| Propagation delay time, /VIN/ falling | tpL | | 240 | 370 | ns | VDD2 = 3.3 V, VREF = 2 V, VOVERDRIVE = 50 mV, CL = 15 pF | 10 |
| Output signal fall time | tf | | 2 | | ns | RPULLUP = 4.7 kΩ, CL = 15 pF | 10 |
## CAD (KiCad official)
- Symbol: `AMC23C12QDWVRQ1`
- Footprint: `Package_SO:SOIC-8_7.5x5.85mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `amc23c12qdwvrq1-etched.step` / `amc23c12qdwvrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `amc23c12qdwvrq1.step` / `amc23c12qdwvrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/amc23c12qdwvrq1.pdf) (43 pp, sha256 `f2ed3aa900354fc3`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/amc23c12qdwvrq1-datasheet.pdf)