component
AMC1351DWVR
Public Made by Adomby adom
Texas Instruments Isolation Amplifiers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAMC1351DWVR
Texas Instruments · Isolation Amplifiers · SOIC-8
AMC1351DWVR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | High-side power supply, specified 3 V to 5.5 V relative to GND1 (absolute maximum 6.5 V); see Power Supply Recommendations for decoupling. |
| 2 | IN | input | Analog input with specified linear full-scale range of -0.25 V to 5 V (absolute maximum -1 V to 15 V). |
| 3 | GND1 | power_in | High-side analog ground reference for the input amplifier; connect to pin 4 and do not leave unconnected. |
| 4 | GND1 | power_in | High-side analog ground, connected to pin 3. |
| 5 | GND2 | power_in | Low-side analog ground reference for the VDD2 supply and outputs. |
| 6 | OUTN | output | Inverting analog output, with capacitive load up to 500 pF to GND2 and resistive load of 1 kΩ minimum. |
| 7 | OUTP | output | Noninverting analog output, with capacitive load up to 500 pF to GND2 and resistive load of 1 kΩ minimum. |
| 8 | VDD2 | power_in | Low-side power supply, specified 3 V to 5.5 V relative to GND2 (absolute maximum 6.5 V); see Power Supply Recommendations for decoupling. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Operational Amplifier/Comparator |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Offset voltage | VOS | -1.5 | 0.3 | 1.5 | mV | TA = 25°C, IN = GND1, 4.5 V ≤ VDD1 ≤ 5.5 V | 8 |
| Offset voltage | VOS | -2.5 | -0.8 | 2.5 | mV | TA = 25°C, IN = GND1, 3.0 V ≤ VDD1 ≤ 5.5 V | 8 |
| Offset voltage thermal drift | TCVOS | -15 | 3 | 15 | µV/°C | IN = GND1 | 8 |
| Input resistance | RIN | 1 | 1.25 | 1.5 | MΩ | 8 | |
| Input resistance thermal drift | TCRIN | 5 | ppm/°C | -40℃ ≤ TA ≤ 85℃ | 8 | ||
| Input capacitance | CIN | 4 | pF | fIN = 275 kHz | 8 | ||
| Nominal gain | 0.4 | V/V | 8 | ||||
| Gain error | EG | -0.2 | 0.05 | 0.2 | % | TA = 25℃ | 8 |
| Gain error thermal drift | TCEG | -35 | 10 | 35 | ppm/°C | 8 | |
| Nonlinearity | -0.02 | 0.003 | 0.02 | % | 8 | ||
| Nonlinearity thermal drift | 0.2 | ppm/°C | 8 | ||||
| Total harmonic distortion | THD | -82 | dB | VIN = 5 VPP, fIN = 10 kHz, BW = 100 kHz | 8 | ||
| Signal-to-noise ratio | SNR | 75 | 79 | dB | VIN = 5 VPP, fIN = 1 kHz, BW = 10 kHz | 8 | |
| Signal-to-noise ratio | SNR | 69 | dB | VIN = 5 VPP, fIN = 10 kHz, BW = 100 kHz | 8 | ||
| Output noise | 250 | µVrms | IN = GND1, BW = 100 kHz | 8 | |||
| PSRR vs VDD1, DC | PSRR | -67 | dB | PSRR vs VDD1, DC | 8 | ||
| PSRR vs VDD2, DC | PSRR | -80 | dB | PSRR vs VDD2, DC | 8 | ||
| PSRR vs VDD1 with ripple | PSRR | -65 | dB | PSRR vs VDD1 with 10-kHz, 100-mV ripple | 8 | ||
| PSRR vs VDD2 with ripple | PSRR | -64 | dB | PSRR vs VDD2 with 10-kHz, 100-mV ripple | 8 | ||
| Output common-mode voltage | VCMout | 1.39 | 1.44 | 1.49 | V | 8 | |
| Clipping differential output voltage | VCLIPout | 2.49 | V | VOUT = (VOUTP, VOUTN), VIN > VClipping | 8 | ||
| Fail-safe differential output voltage | VFail-safe | -2.57 | -2.5 | V | VDD1 undervoltage or VDD1 missing | 8 | |
| Output bandwidth | BW | 275 | 300 | kHz | 8 | ||
| Output resistance | ROUT | 0.2 | Ω | On OUTP or OUTN | 8 | ||
| Output short-circuit current | 14 | mA | On OUTP or OUTN, sourcing or sinking, IN = GND1, outputs shorted to either GND or VDD2 | 8 | |||
| Common-mode transient immunity | CMTI | 100 | 150 | kV/µs | 8 | ||
| VDD1 undervoltage threshold rising | VDD1UV | 2.5 | 2.7 | 2.9 | V | VDD1 rising | 9 |
| VDD1 undervoltage threshold falling | VDD1UV | 2.4 | 2.6 | 2.8 | V | VDD1 falling | 9 |
| VDD2 undervoltage threshold rising | VDD2UV | 2.2 | 2.45 | 2.65 | V | VDD2 rising | 9 |
| VDD2 undervoltage threshold falling | VDD2UV | 1.85 | 2 | 2.2 | V | VDD2 falling | 9 |
| High-side supply current | IDD1 | 6 | 8.1 | mA | 3.0 V < VDD1 < 3.6 V | 9 | |
| High-side supply current | IDD1 | 7 | 9.3 | mA | 4.5 V < VDD1 < 5.5 V | 9 | |
| Low-side supply current | IDD2 | 5.3 | 7.2 | mA | 3.0 V < VDD2 < 3.6 V | 9 | |
| Low-side supply current | IDD2 | 5.9 | 8.1 | mA | 4.5 V < VDD2 < 5.5 V | 9 | |
| Analog settling time | tAS | 500 | 800 | µs | VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to VOUTP and VOUTN valid, 0.1% settling | 10 | |
| Output signal rise time | tr | 1.3 | µs | 10 | |||
| Output signal fall time | tf | 1.3 | µs | 10 | |||
| IN to OUTx signal delay (50%, 10%) | 1 | 1.5 | µs | Unfiltered output | 10 | ||
| IN to OUTx signal delay (50%, 50%) | 1.6 | 2.1 | µs | Unfiltered output | 10 | ||
| IN to OUTx signal delay (50%, 90%) | 2.5 | 3 | µs | Unfiltered output | 10 | ||
| High-side supply voltage | VDD1 | 3 | 5 | 5.5 | V | VDD1 to GND1 | 4 |
| Low-side supply voltage | VDD2 | 3 | 3.3 | 5.5 | V | VDD2 to GND2 | 4 |
| Input voltage before clipping output | VClipping | 6.25 | V | 4 | |||
| Specified linear full-scale voltage | VFSR | -0.25 | 5 | V | 4 | ||
| Capacitive load | CLOAD | 500 | pF | On OUTP or OUTN to GND2 | 4 | ||
| Capacitive load | CLOAD | 250 | pF | OUTP to OUTN | 4 | ||
| Operating ambient temperature | TA | -55 | 125 | °C | Operating ambient temperature | 4 | |
| Specified ambient temperature | TA | -40 | 125 | °C | Specified ambient temperature | 4 | |
| Power-supply voltage high-side | VDD1 | -0.3 | 6.5 | V | VDD1 to GND1 | 4 | |
| Power-supply voltage low-side | VDD2 | -0.3 | 6.5 | V | VDD2 to GND2 | 4 | |
| Analog input voltage | IN | -1 | 15 | V | 4 | ||
| Input current | -10 | 10 | mA | Continuous, any pin except power-supply pins | 4 | ||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 84.6 | °C/W | DWV (SOIC) 8 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 28.3 | °C/W | DWV (SOIC) 8 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 41.1 | °C/W | DWV (SOIC) 8 pins | 5 |
CAD (KiCad official)
- Symbol:
AMC1351DWVR - Footprint:
Package_SO:SOIC-8_7.5x5.85mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
amc1351dwvr-etched.step/amc1351dwvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);amc1351dwvr.step/amc1351dwvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (34 pp, sha256
47be04620cc26e5f, retrieved 2026-10-24, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).