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AMC131M03QDFMRQ1

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TI Analog To Digital Converters (ADCs), SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersamc131m03qdfmrq1factory-2.0.0extractor-text

Verified AMC131M03QDFMRQ1

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AMC131M03QDFMRQ1 · SOIC-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 98-page datasheet
  • ✓distributor: lcsc C19724105, digikey 296-AMC131M03QDFMRQ1TR-ND, mouser 595-AMC131M03QDFMRQ1
  • ✓family: SOIC-20W_7.5x12.8mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6lm5rcg_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.95)
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ amc131m03qdfmrq1.kicad_sym✓ amc131m03qdfmrq1.kicad_mod✓ amc131m03qdfmrq1.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray 1d ago
viewers amc131m03qdfmrq1: viewers · Ray 1d ago
amc131m03qdfmrq1-etched.glb Publish 0.1.0 · Ray 1d ago
amc131m03qdfmrq1-etched.step amc131m03qdfmrq1: factory component page (tier=mfr) · Ray 1d ago
amc131m03qdfmrq1-hero.glb amc131m03qdfmrq1: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
amc131m03qdfmrq1-hero.overlay.json Publish 0.1.0 · Ray 1d ago
amc131m03qdfmrq1.glb Publish 0.1.0 · Ray 1d ago
amc131m03qdfmrq1.kicad_mod Publish 0.1.0 · Ray 1d ago
amc131m03qdfmrq1.kicad_sym Publish 0.1.0 · Ray 1d ago
amc131m03qdfmrq1.lbr Publish 0.1.0 · Ray 1d ago
amc131m03qdfmrq1.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray 1d ago

AMC131M03QDFMRQ1

TI · Analog To Digital Converters (ADCs) · SOIC-20

AMC131M03QDFMRQ1 from TI, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DCDC_OUT power_out High-side output of the DC/DC converter; connect this pin to the HLDO_IN pin.
2 DCDC_HGND power_in High-side ground reference for the DC/DC converter; connect this pin to the HGND pin.
3 HLDO_IN power_in Input of the high-side low-dropout (LDO) regulator; connect this pin to the DCDC_OUT pin.
4 HLDO_OUT power_out Output of the high-side LDO; see Power Supply Recommendations for decoupling.
5 HGND power_in High-side analog signal ground; connect this pin to the DCDC_HGND pin.
6 AIN2P/GPO bidirectional Positive analog input 2, or general-purpose output; absolute input range HGND - 1.3 V to HGND + 2.7 V at gain 1, 2 or 4.
7 AIN12N input Negative analog input shared by channels 1 and 2; absolute input range HGND - 1.3 V to HGND + 2.7 V at gain 1, 2 or 4.
8 AIN1P input Positive analog input 1; absolute input range HGND - 1.3 V to HGND + 2.7 V at gain 1, 2 or 4.
9 AIN0P input Positive analog input 0, to be used for the measurement with the most stringent precision requirements.
10 AIN0N input Negative analog input 0, to be used for the measurement with the most stringent precision requirements.
11 SYNC/RESET input Conversion synchronization or system reset input, active low; input range DGND - 0.3 V to DVDD + 0.3 V.
12 DOUT output Serial data output.
13 DVDD power_in Low-side analog and digital power supply, 3 V to 5.5 V recommended (3.3 V nominal), 6.5 V absolute maximum.
14 DCDC_CAP power_in Low-side input of the DC/DC converter, internally connected to the output of the primary-side LDO; 3.5 V absolute maximum to DGND.
15 DGND power_in Low-side analog and digital ground.
16 DRDY output Data ready output, active low.
17 CLKIN input Main clock input; 4.096 MHz × NDIV typical in high-resolution mode, input range DGND - 0.3 V to DVDD + 0.3 V.
18 SCLK input Serial data clock input; input range DGND - 0.3 V to DVDD + 0.3 V.
19 CS input Chip select input, active low; input range DGND - 0.3 V to DVDD + 0.3 V.
20 DIN input Serial data input; input range DGND - 0.3 V to DVDD + 0.3 V.

Key specifications

Parameter Value
Manufacturer TI
Package SOIC-20
Category Data Converters
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power-supply voltage DVDD to DGND DVDD -0.3 6.5 V 4
Power-supply voltage DCDC_CAP to DGND DCDC_CAP -0.3 3.5 V 4
Analog input voltage AINxP, AINxN -1.6 2.7 V Printed as HGND, 1.6 (min) and HGND + 2.7 (max); values are offsets from HGND 4
Input current continuous, all pins except power-supply pins -10 10 mA Continuous 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -60 150 °C 4
Low-side power supply DVDD to GND VDVDD 3 3.3 5.5 V 4
Absolute input voltage AINxP, AINxN VAINxP, VAINxN -1.3 2.7 V Gain = 1, 2, or 4; printed as HGND, 1.3 to HGND + 2.7; values are offsets from HGND 4
Absolute input voltage AINxP, AINxN VAINxP, VAINxN -1.3 0.9 V Gain = 8, 16, 32, 64, or 128; printed as HGND, 1.3 to HGND + 0.9; values are offsets from HGND 4
Clock divider ratio NDIV 2 12 Signal at CLKIN is divided by NDIV to generate modulator clock 4
External clock frequency, high-resolution mode (multiples of NDIV) fCLKIN 1.4 4.096 4.1 MHz High-resolution mode; printed as 1.4·NDIV, 4.096·NDIV, 4.1·NDIV 4
External clock frequency, low-power mode (multiples of NDIV) fCLKIN 1.4 2.048 2.05 MHz Low-power mode; printed as 1.4·NDIV, 2.048·NDIV, 2.05·NDIV 4
CLKIN duty cycle 40 50 60 % 4
Operating ambient temperature TA -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 68.5 °C/W DFM (SOIC) 20 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 24.6 °C/W 5
Junction-to-board thermal resistance RθJB 53.7 °C/W 5
Input bias current IIB 0.65 0.9 μA AINxP = AINxN = HGND; Gain = 1, 2, or 4 8
Input bias current IIB -1 -0.65 μA AINxP = AINxN = HGND; Gain = 8 to 128 8
Input bias current drift TCIIB -1 0.35 1 nA/°C 8
Integral nonlinearity INL 6 ppm of FSR End-point fit 8
Offset error, channel 0, 1 EO -100 100 330 µV External short, TA = 25°C 8
Offset error, channel 2 EO -100 125 330 µV External short, TA = 25°C 8
Offset error drift, channel 0, 1 TCEO -0.5 0.1 0.5 µV/°C External short 8
Offset error drift, channel 2 TCEO -0.5 0.2 0.5 µV/°C External short 8
Gain error, channel 0 EG -0.2 0.025 0.2 % TA = 25°C, end-point fit 8
Gain error, channel 1, 2 EG -1 0.1 1 % TA = 25°C, end-point fit 8
Gain error drift vs temperature TCEG 8 25 ppm/°C Including internal reference error 8
Total harmonic distortion THD -102 -94 dB fIN = 50 Hz or 60 Hz (up to 5 harmonics), VIN = -0.5 dBFS 9
Common-mode transient immunity CMTI 100 150 V/ns 9
Logic input level, low VIL 0.2 V Printed as 0.2 DVDD (max) 9
Logic input level, high VIH 0.8 V Printed as 0.8 DVDD (min) 9
Input current IIN -1 1 µA DGND < VDigital Input < DVDD 9
Low-side supply current, high-resolution mode IDVDD 19.5 24 mA High-resolution mode 10
Low-side supply current, low-power mode IDVDD 16 21 mA Low-power mode, fCLKIN = 4.096 MHz 10
Low-side supply current, standby mode IDVDD 160 210 µA Standby mode, all channels disabled, no clock applied 10
High-side LDO output voltage, no load VHLDO_OUT 2.6 2.9 3.2 V HLDO_OUT to HGND, no external load, any channel enabled 10
High-side LDO output voltage, 1-mA load VHLDO_OUT 2.4 2.8 3.1 V HLDO_OUT to HGND, 1-mA external load on HLDO_OUT, any channel enabled 10
SCLK period tc(SC) 40 ns 3.0 V ≤ DVDD ≤ 5.5 V 11
Delay time, CS rising edge to DOUT high impedance tp(CSDOZ) 75 ns 3.0 V ≤ DVDD ≤ 5.5 V 11
Power-on-reset time tPOR 250 µs Measured from supplies at 90% 11

CAD (KiCad official)

  • Symbol: AMC131M03QDFMRQ1
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: amc131m03qdfmrq1-etched.step / amc131m03qdfmrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amc131m03qdfmrq1.step / amc131m03qdfmrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI datasheet (98 pp, sha256 96afe9192171845f, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF