component
AMC131M03DFMR
Public Made by Adomby adom
TEXAS INSTRUMENTS Global Sourcing Parts, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AMC131M03DFMR
TEXAS INSTRUMENTS · Global Sourcing Parts · SOIC-20
AMC131M03DFMR from TEXAS INSTRUMENTS, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DCDC_OUT | power_out | High-side output of the DC/DC converter, which must be connected to the HLDO_IN pin. |
| 2 | DCDC_HGND | power_in | High-side ground reference for the DC/DC converter, which must be connected to the HGND pin. |
| 3 | HLDO_IN | power_in | Input of the high-side low-dropout regulator, which must be connected to the DCDC_OUT pin. |
| 4 | HLDO_OUT | power_out | Output of the high-side low-dropout regulator. |
| 5 | HGND | power_in | High-side analog signal ground, which must be connected to the DCDC_HGND pin. |
| 6 | AIN2P/GPO | passive | Positive analog input 2, or general-purpose output. |
| 7 | AIN12N | passive | Negative analog input 1 and 2. |
| 8 | AIN1P | passive | Positive analog input 1. |
| 9 | AIN0P | passive | Positive analog input 0; use AIN0P and AIN0N for the measurement with the most stringent precision requirements. |
| 10 | AIN0N | passive | Negative analog input 0; use together with AIN0P for the measurement with the most stringent precision requirements. |
| 11 | SYNC/RESET | input | Conversion synchronization or system reset input, active low. |
| 12 | DOUT | output | Serial data output. |
| 13 | DVDD | power_in | Low-side analog and digital power supply, specified from 3 V to 5.5 V. |
| 14 | DCDC_CAP | power_in | Low-side input of the DC/DC converter, internally connected to the output of the primary-side LDO. |
| 15 | DGND | power_in | Low-side analog and digital ground. |
| 16 | DRDY | output | Data ready output, active low. |
| 17 | CLKIN | input | Main clock input. |
| 18 | SCLK | input | Serial data clock input. |
| 19 | CS | input | Chip select input, active low. |
| 20 | DIN | input | Serial data input. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | SOIC-20 |
| Category | Global Sourcing Parts |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input bias current | IIB | 0.65 | 0.9 | µA | AINxP = AINxN = HGND; Gain = 1, 2, or 4 | 8 | |
| Input bias current | IIB | -1 | -0.65 | µA | AINxP = AINxN = HGND; Gain = 8 to 128 | 8 | |
| Input bias current drift | TCIIB | -1 | 0.35 | 1 | nA/°C | 8 | |
| Input offset current | IIO | -15 | 15 | nA | IIO = IIBP, IIBN | 8 | |
| Offset error (input referred) | EO | -100 | 330 | µV | Channel 0,1, external short, TA = 25°C | 8 | |
| Offset error (global-chop mode) | EO | -100 | 6 | 100 | µV | Global-chop mode, channel 0, 1, default global-chop delay, external short, TA = 25°C | 8 |
| Offset error (global-chop mode) | EO | -120 | 42 | 120 | µV | Global-chop mode, channel 2, default global-chop delay, external short, TA = 25°C | 8 |
| Offset error drift vs temperature | TCEO | -0.5 | 0.1 | 0.5 | µV/°C | Channel 0, 1, external short | 8 |
| Offset error drift vs temperature | TCEO | -0.5 | 0.2 | 0.5 | µV/°C | Channel 2, external short | 8 |
| Offset error drift vs temperature | TCEO | -0.3 | 0.1 | 0.3 | µV/°C | Global-chop mode channel 0, 1, external short | 8 |
| Gain error | EG | -0.2 | 0.025 | 0.2 | % | Channel 0, TA = 25°C, end-point fit | 8 |
| Gain error | EG | -1 | 0.1 | 1 | % | Channel 1, 2, TA = 25°C, end-point fit | 8 |
| Gain error drift vs temperature | TCEG | 8 | 25 | ppm/°C | Including internal reference error | 8 | |
| Integral nonlinearity | INL | 6 | ppm of FSR | End-point fit | 8 | ||
| Supply voltage range | VDVDD | 3 | 3.3 | 5.5 | V | DVDD to GND | 4 |
| Absolute input voltage, gain 1, 2, or 4 | VAINxP, VAINxN | -1.3 | 2.7 | V | Gain = 1, 2, or 4; relative to HGND | 4 | |
| Absolute input voltage, gain 8 to 128 | VAINxP, VAINxN | -1.3 | 0.9 | V | Gain = 8, 16, 32, 64, or 128; relative to HGND | 4 | |
| Clock divider ratio | NDIV | 2 | 12 | Signal at CLKIN divided by NDIV to generate modulator clock | 4 | ||
| Clock duty cycle | 40 | 50 | 60 | % | External clock source at CLKIN | 4 | |
| Operating ambient temperature | TA | -40 | 125 | °C | Operating ambient temperature | 4 | |
| Power-supply voltage DVDD | -0.3 | 6.5 | V | DVDD to DGND | 4 | ||
| Power-supply voltage DCDC_CAP | -0.3 | 3.5 | V | DCDC_CAP to DGND | 4 | ||
| Analog input voltage AINxP, AINxN | -1.6 | 2.7 | V | Relative to HGND | 4 | ||
| Digital input voltage CS, CLKIN, DIN, SCLK, SYNC/RESET | -0.3 | V | Relative to DGND; maximum is DVDD + 0.3 V as printed | 4 | |||
| Input current, continuous, all pins except power-supply pins | -10 | 10 | mA | Continuous | 4 | ||
| Junction temperature | TJ | 150 | °C | Junction | 4 | ||
| Storage temperature | Tstg | -60 | 150 | °C | Storage | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 68.5 | °C/W | DFM (SOIC) 20 pins | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 24.6 | °C/W | DFM (SOIC) 20 pins | 5 | ||
| Junction-to-board thermal resistance | RθJB | 53.7 | °C/W | DFM (SOIC) 20 pins | 5 | ||
| Junction-to-top characterization parameter | ΨJT | 17.1 | °C/W | DFM (SOIC) 20 pins | 5 | ||
| Junction-to-board characterization parameter | ΨJB | 50.9 | °C/W | DFM (SOIC) 20 pins | 5 | ||
| Common-mode rejection ratio | CMRR | 110 | dB | fIN = 0 Hz, VCM min ≤ VIN ≤ VCM max | 9 | ||
| Total harmonic distortion | THD | -102 | -94 | dB | fIN = 50 Hz or 60 Hz (up to 5 harmonics), VIN = -0.5 dBFS | 9 | |
| Common-mode transient immunity | CMTI | 100 | V/ns | 9 | |||
| Temperature measurement error | -3 | 3 | °C | Internal temperature sensor, TA = 25°C, gain = 8 | 9 | ||
| Temperature measurement error | -5 | 5 | °C | Internal temperature sensor, across temperature, gain = 8 | 9 | ||
| Logic input current | IIN | -1 | 1 | µA | DGND < VDigital Input < DVDD | 9 | |
| Output load capacitance | CLOAD | 15 | 30 | pF | 9 | ||
| Low-side supply current, high-resolution mode | IDVDD | 19.5 | 24 | mA | High-resolution mode | 10 | |
| Low-side supply current, low-power mode | IDVDD | 16 | 21 | mA | Low-power mode, fCLKIN = 4.096 MHz | 10 | |
| Standby supply current | IDVDD | 160 | 210 | µA | Standby mode, all channels disabled, no clock applied | 10 | |
| High-side LDO output voltage, no load | VHLDO_OUT | 2.6 | 2.9 | 3.2 | V | HLDO_OUT to HGND, no external load, any channel enabled | 10 |
| High-side LDO output voltage, 1-mA load | VHLDO_OUT | 2.4 | 2.8 | 3.1 | V | HLDO_OUT to HGND, 1-mA external load on HLDO_OUT, any channel enabled | 10 |
| Pulse duration, CLKIN low | tw(CLL) | 49 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Pulse duration, CLKIN high | tw(CLH) | 49 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| SCLK period | tc(SC) | 40 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Pulse duration, SCLK low | tw(SCL) | 20 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Pulse duration, SCLK high | tw(SCH) | 20 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Setup time, DIN valid before SCLK falling edge | tsu(DI) | 5 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Hold time, DIN valid after SCLK falling edge | th(DI) | 8 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Setup time, SYNC/RESET valid before CLKIN falling edge | tsu(SY) | 10 | ns | 3.0 V ≤ DVDD ≤ 5.5 V | 11 | ||
| Input bias current, supply-referenced single-ended impedance | RIN | 250 | kΩ | AINxN = HGND, gain = 1, 2, or 4 | 8 | ||
| Single-ended input impedance | RIN | 0.5 | MΩ | AINxN = HGND, gain = 8 to 128 | 8 | ||
| Differential input impedance | ZIND | 275 | kΩ | (AINxN + AINxP) / 2 = HGND, Gain = 1, 2, or 4 | 8 | ||
| Differential input impedance | ZIND | 1 | MΩ | (AINxN + AINxP) / 2 = HGND, Gain = 8 to 128 | 8 | ||
| Resolution | 24 | Bits | 8 | ||||
| SPI start-up time | 0.3 | ms | Measured from supplies at 90% to SPI interface ready to accept data | 8 | |||
| Converter start-up time | 1 | ms | Measured from DCDC enable bit set to first DRDY falling edge with data settled to 0.1% (CLKIN running) | 8 | |||
| Input-referred noise | EN | 10 | µVRMS | 9 | |||
| Dynamic range, gain = 1 | DR | 98 | dB | Gain = 1 | 9 | ||
| Dynamic range, gain = 32, channel 0 | DR | 80 | dB | Gain = 32, channel 0 | 9 | ||
| Crosstalk | -120 | dB | From one channel to any other; fIN = 50 Hz or 60 Hz at AINxP while AINxN = HGND | 9 | |||
| Signal-to-noise ratio, gain = 1 | SNR | 98 | dB | fIN = 50 Hz or 60 Hz, gain = 1, VIN = -0.5 dBFS, normalized | 9 | ||
| Signal-to-noise ratio, gain = 32, channel 0 | SNR | 80 | dB | fIN = 50 Hz or 60 Hz, gain = 32, channel 0, VIN = -0.5 dBFS, normalized | 9 | ||
| Spurious-free dynamic range | SFDR | 105 | dB | fIN = 50 Hz or 60 Hz, VIN = -0.5 dBFS | 9 | ||
| Internal reference voltage | VREF | 1.2 | V | 9 | |||
| Internal temperature sensor voltage | 80.5 | mV | Internal temperature sensor, TA = 25°C, gain = 8 | 9 | |||
| Internal temperature sensor temperature coefficient | 265 | µV/°C | Internal temperature sensor, TA = 25°C, gain = 8 | 9 | |||
| External temperature sensor input impedance | 8 | MΩ | External temperature sensor, TA = 25°C, gain = 1, 2, or 4 | 9 | |||
| Total unadjusted error | TUE | 0.3 | % FSR | External temperature sensor, TA = 25°C, gain = 1 | 9 | ||
| Input capacitance | CIN | 1 | pF | 9 | |||
| High-side GPO output impedance, driving 0 | RGPO | 100 | Ω | Driving 0 | 9 | ||
| High-side GPO output impedance, driving 1 | RGPO | 115 | Ω | Driving 1 | 9 | ||
| High-side GPO load current | IGPO | 1 | mA | 9 | |||
| Power dissipation, high-resolution mode | PD | 64 | mW | High-resolution mode | 10 | ||
| Power dissipation, low-power mode | PD | 53 | mW | Low-power mode, fCLKIN = 4.096 MHz | 10 | ||
| Power dissipation, standby mode | PD | 525 | µW | Standby mode, all channels disabled, no clock applied | 10 | ||
| DC/DC output voltage | VDCDC_OUT | 3 | V | DCDC_OUT to HGND, all channels enabled, TA = 25°C | 10 | ||
| High-side supply current for auxiliary circuitry | IH | 1 | mA | Load connected from HLDO_OUT to HGND | 10 | ||
| Power-on-reset time | tPOR | 250 | µs | Measured from supplies at 90% | 12 | ||
| Register default acquisition time | tREGACQ | 5 | µs | 12 |
CAD (KiCad official)
- Symbol:
AMC131M03DFMR - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20 (KiCad packages3D, STEP)
- 3D model files:
amc131m03dfmr-etched.step/amc131m03dfmr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);amc131m03dfmr.step/amc131m03dfmr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TEXAS INSTRUMENTS datasheet (100 pp, sha256
e6502c3649788095, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).