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AMC131M02DFMR

Texas Instruments · IC · SOIC-20

AMC131M02DFMR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DCDC_OUT power_out High-side output of the DC/DC converter; connect this pin to the HLDO_IN pin.
2 DCDC_HGND power_in High-side ground reference for the DC/DC converter; connect this pin to the HGND pin.
3 HLDO_IN power_in Input of the high-side low-dropout (LDO) regulator; connect this pin to the DCDC_OUT pin.
4 HLDO_OUT power_out Output of the high-side LDO.
5 HGND power_in High-side analog signal ground; connect this pin to the DCDC_HGND pin.
6 GPO output General-purpose digital output.
7 AIN1N input Negative analog input 1.
8 AIN1P input Positive analog input 1.
9 AIN0P input Positive analog input 0; use AIN0P and AIN0N for the measurement with the most stringent precision requirements.
10 AIN0N input Negative analog input 0; use AIN0P and AIN0N for the measurement with the most stringent precision requirements.
11 SYNC/RESET input Conversion synchronization or system reset input, active low.
12 DOUT output Serial data output.
13 DVDD power_in Low-side analog and digital power supply, 3 V to 5.5 V recommended operating range.
14 DCDC_CAP power_in Low-side input of the DC/DC converter, internally connected to the output of the primary-side LDO; absolute maximum 3.5 V to DGND.
15 DGND power_in Low-side analog and digital ground.
16 DRDY output Data ready output, active low.
17 CLKIN input Main clock input.
18 SCLK input Serial data clock input.
19 CS input Chip select input, active low.
20 DIN input Serial data input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power-supply voltage DVDD to DGND -0.3 6.5 V 4
Power-supply voltage DCDC_CAP to DGND -0.3 3.5 V 4
Analog input voltage AINxP, AINxN -1.6 2.7 V 4
Digital input voltage CS, CLKIN, DIN, SCLK, SYNC/RESET -0.3 V 4
Input current, continuous, all pins except power-supply pins -10 10 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -60 150 °C 4
Low-side power supply DVDD to GND VDVDD 3 3.3 5.5 V DVDD to GND 4
Absolute input voltage, gain 1, 2, or 4 VAINxP, VAINxN -1.3 2.7 V Gain = 1, 2, or 4 4
Absolute input voltage, gain 8 to 128 VAINxP, VAINxN -1.3 0.9 V Gain = 8, 16, 32, 64, or 128 4
Clock divider ratio NDIV 2 12 Signal at CLKIN is divided by NDIV to generate modulator clock 4
Duty cycle, external clock at CLKIN 40 50 60 % 4
Operating ambient temperature TA -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 68.5 °C/W 5
Junction-to-case (top) thermal resistance RθJC(top) 24.6 °C/W 5
Junction-to-board thermal resistance RθJB 53.7 °C/W 5
Junction-to-top characterization parameter ΨJT 17.1 °C/W 5
Junction-to-board characterization parameter ΨJB 50.9 °C/W 5
Input bias current, gain 1, 2, or 4 IIB 0.65 0.9 µA AINxP = AINxN = HGND; IIB = (IIBP + IIBN) / 2, Gain = 1, 2, or 4 8
Input bias current, gain 8 to 128 IIB -1 -0.65 µA AINxP = AINxN = HGND; IIB = (IIBP + IIBN) / 2, Gain = 8 to 128 8
Input bias current drift TCIIB -1 0.35 1 nA/°C 8
Input offset current IIO -15 15 nA IIO = IIBP, IIBN 8
Offset error (input referred) EO -100 100 330 µV External short, TA = 25°C 8
Offset error (input referred), global-chop mode EO -100 6 100 µV Global-chop mode, default global-chop delay, external short, TA = 25°C 8
Offset error drift vs temperature TCEO -0.5 0.1 0.5 µV/°C External short 8
Offset error drift vs temperature, global-chop mode TCEO -0.3 0.1 0.3 µV/°C Global-chop mode, external short 8
Gain error, channel 0 EG -0.2 0.025 0.2 % Channel 0, TA = 25°C, end-point fit 8
Gain error, channel 1 EG -1 0.1 1 % Channel 1, TA = 25°C, end-point fit 8
Gain error drift vs temperature TCEG 8 25 ppm/°C Including internal reference error 8
Digital input current IIN -1 1 µA DGND < VDigital Input < DVDD 9
Low-side supply current, high-resolution mode IDVDD 18 23 mA High-resolution mode 9
Low-side supply current, low-power mode IDVDD 15.5 20 mA Low-power mode 9
Low-side supply current, standby mode IDVDD 160 210 µA Standby mode, all channels disabled, no clock applied 9
High-side LDO output voltage, no external load VHLDO_OUT 2.6 2.9 3.2 V HLDO_OUT to HGND, no external load, any channel enabled 9
High-side LDO output voltage, 1-mA external load VHLDO_OUT 2.4 2.8 3.1 V HLDO_OUT to HGND, 1-mA external load on HLDO_OUT, any channel enabled 9

CAD (KiCad official)

  • Symbol: AMC131M02DFMR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: amc131m02dfmr-etched.step / amc131m02dfmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amc131m02dfmr.step / amc131m02dfmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (89 pp, sha256 b40fed492cf1fefa, retrieved 2026-11-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF