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AMC130M03DFMR

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Texas Instruments Isolated ADCs With Power, SOIC-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AMC130M03DFMR

Texas Instruments · Isolated ADCs With Power · SOIC-20

AMC130M03DFMR from Texas Instruments, in a SOIC-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DCDC_OUT power_out High-side output of the DC/DC converter; connect this pin to the HLDO_IN pin.
2 DCDC_HGND power_in High-side ground reference for the DC/DC converter; connect this pin to the HGND pin.
3 HLDO_IN power_in Input of the high-side low-dropout (LDO) regulator; connect this pin to the DCDC_OUT pin.
4 HLDO_OUT power_out Output of the high-side LDO.
5 HGND power_in High-side analog signal ground; connect this pin to the DCDC_HGND pin.
6 AIN2P/GPO bidirectional Positive analog input 2, or general-purpose output.
7 AIN12N input Negative analog input 1 and 2.
8 AIN1P input Positive analog input 1.
9 AIN0P input Positive analog input 0; use with AIN0N for the measurement with the most stringent precision requirements.
10 AIN0N input Negative analog input 0; use with AIN0P for the measurement with the most stringent precision requirements.
11 SYNC/RESET input Conversion synchronization or system reset input, active low.
12 DOUT output Serial data output.
13 DVDD power_in Low-side analog and digital power supply, 3 V to 5.5 V recommended operating range.
14 DCDC_CAP passive Low-side input of the DC/DC converter, internally connected to the output of the primary-side LDO.
15 DGND power_in Low-side analog and digital ground.
16 DRDY output Data ready output, active low.
17 CLKIN input Main clock input.
18 SCLK input Serial data clock input.
19 CS input Chip select input, active low.
20 DIN input Serial data input.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-20
Category Signal Isolation Devices
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power-supply voltage DVDD to DGND DVDD -0.3 6.5 V 4
Power-supply voltage DCDC_CAP to DGND DCDC_CAP -0.3 3.5 V 4
Analog input voltage AINxP, AINxN -1.6 2.7 V Relative to HGND (HGND, 1.6 to HGND + 2.7) 4
Digital input voltage -0.3 0.3 V CS, CLKIN, DIN, SCLK, SYNC/RESET; DGND, 0.3 to DVDD + 0.3 4
Input current -10 10 mA Continuous, all pins except power-supply pins 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -60 150 °C 4
ESD HBM V(ESD) -2000 2000 V HBM per ANSI/ESDA/JEDEC JS-001 4
ESD CDM V(ESD) -1000 1000 V CDM per ANSI/ESDA/JEDEC JS-002 4
Low-side power supply VDVDD 3 3.3 5.5 V DVDD to GND 4
Clock divider ratio NDIV 2 12 Signal at CLKIN is divided by NDIV to generate modulator clock 4
External clock frequency, high-resolution mode fCLKIN 1.4 4.096 4.1 MHz High-resolution mode; values printed as 1.4·NDIV, 4.096·NDIV, 4.1·NDIV 4
External clock frequency, low-power mode fCLKIN 1.4 2.048 2.05 MHz Low-power mode; values printed as 1.4·NDIV, 2.048·NDIV, 2.05·NDIV 4
Clock duty cycle 40 50 60 % 4
Operating ambient temperature TA -40 125 °C 4
Junction-to-ambient thermal resistance RθJA 68.5 °C/W DFM (SOIC) 20 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 24.6 °C/W 5
Junction-to-board thermal resistance RθJB 53.7 °C/W 5
Input bias current, gain 1, 2, 4 IIB 0.65 0.9 μA AINxP = AINxN = HGND; IIB = (IIBP + IIBN) / 2, Gain = 1, 2, or 4 8
Input bias current, gain 8 to 128 IIB -1 -0.65 μA AINxP = AINxN = HGND; IIB = (IIBP + IIBN) / 2, Gain = 8 to 128 8
Input bias current drift TCIIB -1 0.35 1 nA/°C Specified by design and characterization; typ printed ±0.35 8
Offset error, channel 0,1 EO -100 100 330 µV Channel 0,1, external short, TA = 25°C; typ printed ±100 8
Offset error, channel 2 EO -100 125 330 µV Channel 2, external short, TA = 25°C; typ printed ±125 8
Offset error, global-chop, channel 0,1 EO -100 6 100 µV Global-chop mode, channel 0, 1, default global-chop delay, external short, TA = 25°C 8
Offset error, global-chop, channel 2 EO -120 42 120 µV Global-chop mode, channel 2, default global-chop delay, external short, TA = 25°C 8
Offset error drift, channel 0,1 TCEO -0.5 0.1 0.5 µV/°C Channel 0, 1, external short 8
Offset error drift, channel 2 TCEO -0.5 0.2 0.5 µV/°C Channel 2, external short 8
Offset error drift, global-chop channel 0,1 TCEO -0.3 0.1 0.3 µV/°C Global-chop mode channel 0, 1, external short 8
Offset error drift, global-chop channel 2 TCEO -0.3 0.1 0.3 µV/°C Global-chop mode channel 2, external short 8
Gain error, channel 0 EG -0.2 0.025 0.2 % Channel 0, TA = 25°C, end-point fit 8
Gain error, channel 1, 2 EG -1 0.1 1 % Channel 1, 2, TA = 25°C, end-point fit 8
Gain error drift vs temperature TCEG 8 25 ppm/°C Including internal reference error 8
Integral nonlinearity INL 6 ppm of FSR End-point fit 8
Total harmonic distortion THD -102 -94 dB fIN = 50 Hz or 60 Hz (up to 5 harmonics), VIN = -0.5 dBFS 9
Common-mode transient immunity CMTI 100 150 V/ns 9
Logic input level, low VIL 0 0.2 V DGND to 0.2 DVDD 9
Logic input level, high VIH 0.8 1 V 0.8 DVDD to DVDD 9
Logic output level, low VOL 0.2 V IOL = -1 mA; max 0.2 DVDD 9
Logic output level, high VOH 0.8 V IOH = 1 mA; min 0.8 DVDD 9
Input current IIN -1 1 µA DGND < VDigital Input < DVDD 9
Output load capacitance CLOAD 15 30 pF 9
Low-side supply current, high-resolution mode IDVDD 19.5 24 mA High-resolution mode 9
Low-side supply current, low-power mode IDVDD 16 21 mA Low-power mode, fCLKIN = 4.096 MHz 9
Low-side supply current, standby IDVDD 160 210 µA Standby mode, all channels disabled, no clock applied 9
High-side LDO output voltage, no load VHLDO_OUT 2.6 2.9 3.2 V HLDO_OUT to HGND, no external load, any channel enabled 10
High-side LDO output voltage, 1-mA load VHLDO_OUT 2.4 2.8 3.1 V HLDO_OUT to HGND, 1-mA external load on HLDO_OUT, any channel enabled 10
Power dissipation, high-resolution mode PD 64 mW High-resolution mode 10
SCLK period tc(SC) 40 ns 3.0 V ≤ DVDD ≤ 5.5 V 11
Setup time, DIN valid before SCLK falling edge tsu(DI) 5 ns 3.0 V ≤ DVDD ≤ 5.5 V 11
Hold time, DIN valid after SCLK falling edge th(DI) 8 ns 3.0 V ≤ DVDD ≤ 5.5 V 11
Propagation delay, SCLK rising edge to valid new DOUT tp(SCDO) 20 ns 3.0 V ≤ DVDD ≤ 5.5 V 11
Power-on-reset time tPOR 250 µs Measured from supplies at 90% 11

CAD (KiCad official)

  • Symbol: AMC130M03DFMR
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20 (KiCad packages3D, STEP)
  • 3D model files: amc130m03dfmr-etched.step / amc130m03dfmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); amc130m03dfmr.step / amc130m03dfmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (97 pp, sha256 a76478a67e2909cc, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF