# AM26LV32EIPWR

**Texas Instruments** · Buffer/Driver/Transceiver · TSSOP-16

AM26LV32EIPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1B | input | Channel 1 RS-422/RS-485 differential input (inverting). Common-mode range −7 V to 7 V; differential threshold ±200 mV with 35 mV hysteresis. |
| 2 | 1A | input | Channel 1 RS-422/RS-485 differential input (noninverting). Paired with 1B; supports partial-power-down (Ioff) operation. |
| 3 | 1Y | tri_state | Channel 1 logic-level receiver output. 3-state; VOH ≥ 2.4 V at IOH = −5 mA, VOL ≤ 0.5 V at IOL = 5 mA. High-Z when disabled by G/G̅. |
| 4 | G | input | Active-high enable input for all four receiver outputs. Accepts up to 5-V logic with 3.3-V supply. Both G high and G̅ low required to enable outputs. |
| 5 | 2Y | tri_state | Channel 2 logic-level receiver output. 3-state; controlled by G/G̅ enables. |
| 6 | 2A | input | Channel 2 RS-422/RS-485 differential input (noninverting). |
| 7 | 2B | input | Channel 2 RS-422/RS-485 differential input (inverting). |
| 8 | GND | power_in | Device ground reference. |
| 9 | 3B | input | Channel 3 RS-422/RS-485 differential input (inverting). |
| 10 | 3A | input | Channel 3 RS-422/RS-485 differential input (noninverting). |
| 11 | 3Y | tri_state | Channel 3 logic-level receiver output. 3-state; controlled by G/G̅ enables. |
| 12 | G̅ | input | Active-low enable input for all four receiver outputs. Outputs are enabled when G is high AND G̅ is low; otherwise outputs are high-impedance. |
| 13 | 4Y | tri_state | Channel 4 logic-level receiver output. 3-state; controlled by G/G̅ enables. |
| 14 | 4A | input | Channel 4 RS-422/RS-485 differential input (noninverting). |
| 15 | 4B | input | Channel 4 RS-422/RS-485 differential input (inverting). |
| 16 | VCC | power_in | Positive supply. Recommended 3.0 V to 3.6 V (3.3 V nominal); ICC 8 mA typ, 17 mA max. Bypass locally with 100-nF ceramic. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |

## Ordering variants

Same part, different packaging or reel option.

- `AM26LV32EIPWR`
- `AM26LV32EIPWRD`
- `AM26LV32EIPWRDR`
- `AM26LV32EIPWRNS`
- `AM26LV32EIPWRNSR`
- `AM26LV32EIPWRRGY`
- `AM26LV32EIPWRRGYR`

## CAD (KiCad official)

- Symbol: `AM26LV32EIPWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `am26lv32eipwr-etched.step` / `am26lv32eipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `am26lv32eipwr.step` / `am26lv32eipwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/am26lv32ei.pdf) (26 pp, sha256 `f0d080894b8d2fc4`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/am26lv32eipwr-datasheet.pdf)