Altium Bridge: AI for Altium Designer

@@ -1,5 +1,19 @@ # Changelog +## 0.2.66 (2026-10-23)+**Multi-part symbols end to end.** 0.2.65 could make a dual op-amp, but the sheet read part 2 back as part 1, so annotate could not number it.+- `altium_sch_place_part {partId}`: the placed part carries the symbol's part count (it was clamped to one part), and every part's objects with their own part numbers, the way Altium's own placement builds it. Shared power pins are no longer copied onto each part.+- `altium_schematic_data`: each part reports `partCount`, and lists only its own pins plus the shared ones, each with `part`, `hidden` and `hiddenNet`. It used to list every pin of the symbol, or the pins of other display modes.+- `altium_annotate` numbers multi-part `?` parts: the parts of one symbol on a sheet share a number (U4A + U4B), grouped top-left first. They used to be left to Altium's Tools > Annotation.+- `altium_create_symbol`: a pin's 6th field hides it on a net (`8,V+,left,300,0,VCC`). Visible shared power pins make the compiler report duplicate pins and duplicate net names (measured, also with Altium's own placement); hidden, the project compiles clean. Pins given as objects (`{number, name, side, offsetMil?, part?, hiddenNet?}`) work. They used to reach the agent as their JSON text and come out as one garbage pin, which the battery did not notice.+- New verb `altium_board_features`: mounting holes (at points, or `{corners:{inset}}`; unplated bare holes or plated on a net), fiducials (1 mm copper, 2 mm mask opening, no paste) and a stitching-via grid on a net, computed by the bridge from the board: clear of other nets' copper, every pad, the edge, this call's holes and fiducials, and out from under parts. `dryRun` returns the plan. Measured on the battery board: 4 holes, 2 fiducials and 38 GND vias in one undo step, every one landed; the fiducials read back mask +0.5 mm and paste -1 mm. The reply's `holeRule` says how to widen a fab hole-size rule that stops below the holes. 174 verbs.+- A pad's mask and paste expansion are written through the pad cache. Writing `Pad.SolderMaskExpansion` directly crashed Altium Develop (an access violation in ScriptingSystem.DLL); the release lint now refuses it, and `MidXSize` stays refused.+- Altium's crash-report box ("Access violation ...", TShowException) is catalogued. The bridge closes it like its title-bar X and never presses Send and Close, which would send a report to Altium. (Escape closed it on the laptop; the close path in the bridge has not met a live crash box yet.)+- `altium_sch_connect {kind:"noerc"}`: a No ERC marker on a pin's outer end, for a pin left open on purpose (no wire, no net). Measured: two markers on U3, compile reported neither (a marker placed off any pin was reported as "Floating No ERC").+- Verb battery: `sch_connect` adds a No ERC marker (3 connections must land).+- Verb battery: `board_features` on the lane board (2 mm corner holes, a fiducial, 4 stitching vias; all 9 must land).+- Verb battery: `create_symbol` makes a dual op-amp from pin objects with hidden power pins and checks all 8 pins and both parts arrive.+ ## 0.2.65 (2026-10-22) **Everything coffeenmusic/altium-mcp does, and the Designer + Develop machine.** Colby asked to compare with that open-source Altium MCP server (43 tools) and make sure we do everything it does. The gaps: - `altium_selection {select?}`: what is selected in the current board (mm, rotation, side, footprint, size) or sheet (mils), or select exactly the named parts to show the user.

@@ -11,7 +11,7 @@ and the verb prefix `altium_`.  ## What it can do -Tested on Altium Designer 26.11.1 and Altium Designer Develop. 173 verbs; each row names the ones+Tested on Altium Designer 26.11.1 and Altium Designer Develop. 174 verbs; each row names the ones behind it (prefix `altium_`).  | Area | What the AI can do | Verbs |@@ -23,6 +23,7 @@ behind it (prefix `altium_`). | Checks | Compile and ERC with the Messages panel read back, DRC with each violation's location, a 14-check design review, schematic-to-board cross-check | `compile`, `run_erc`, `run_drc`, `routing_drc`, `review_board`, `cross_check` | | Schematic to board | Update PCB with the whole change order previewed row by row first, keeping board-only parts, net classes and rules | `update_pcb` | | Board setup | Build a board from a netlist, shape the outline, edit the stack-up (add planes and inner layers, set copper, dielectrics and total thickness), write a fab's design rules, add scoped rules, net classes and differential pairs | `build_board`, `set_outline`, `board_outline`, `layer_stack`, `set_design_rules`, `add_rule`, `net_classes`, `diff_pairs` |+| Board furniture | Mounting holes (at points or the corners), fiducials with a mask opening and no paste, a stitching-via grid that keeps clear of other nets, pads and parts | `board_features` | | Placement | Move and rotate parts or shift them by an offset (read back to 0.001 mm), find free space for a part near another, suggest rotations that shorten connections, copy one channel's layout to the others, swap footprints, read or set the selection | `move_parts`, `find_space`, `check_orientation`, `replicate_layout`, `swap_footprint`, `selection` | | Routing and copper | Route a net with waypoints and vias, run Altium's autorouter, rip up nets, resize routed tracks, pour polygons with keepouts, repour, place vias, clean up the silkscreen | `route_net`, `autoroute`, `ripup_nets`, `set_track_width`, `apply_pours`, `repour`, `place_vias`, `apply_silkscreen` | | BOM | Bill of materials straight from Altium, grouped by MPN with a variant applied, JLCPCB / Mouser / DigiKey files, ordering gaps flagged; write parameters back to the sheets; assembly variants | `bom`, `sheet_params`, `variants` |@@ -47,7 +48,7 @@ Current, heat and EMC analysis of an Altium board runs through [AI Flow](https:/  Altium Designer is the user's **host app**. The bridge *detects* an existing install (`%ProgramFiles%\Altium\AD*\X2.EXE`), launches it in the background, bootstraps a **resident-DelphiScript agent** inside it (the REPL lane), and hands the AI 173 `altium_*` verbs.+DelphiScript agent** inside it (the REPL lane), and hands the AI 174 `altium_*` verbs.  - **Page / docs:** https://wiki.adom.inc/adom/altium-bridge - **Bridge SDK:** https://wiki.adom.inc/adom/adom-bridge-sdk@@ -155,7 +156,7 @@ A halted engine (DelphiScript runtime errors are modal) recovers with `altium_ag **Board & schematic introspection (0.1.11):** `list_designators`, `component_data`, `component_pins`, `list_nets`, `net_connections`, `layers`, `copper_layers`, `read_rules`, `set_layer_visibility`, `footprint_primitives`, `schematic_data` — read the live design as data (pads→nets, rules, layers, sheet components with pins), all in tens of milliseconds, no dialogs.  -All 173 verbs (prefix `altium_`). Call `altium_describe` for the live catalog.+All 174 verbs (prefix `altium_`). Call `altium_describe` for the live catalog.  **Readiness & lifecycle** — `readiness`, `status`, `launch`, `close`, `diagnostics`, `progress`, `agent_start/_stop/_status/_recover`, `license`, `signin_status`, `connect_workspace`, `uninstall`.

@@ -33,6 +33,7 @@ Say **altium** to reach this bridge. Every verb returns `success`, a stable `err | Check the design | `altium_compile` (ERC), `altium_run_drc`, `altium_routing_drc`, `altium_review_board`, `altium_cross_check`, `altium_read_rules` (rule values) | | Find a part on the sheet or board | `altium_sch_zoom`, `altium_zoom_to` | | Place, route, pour, silkscreen a board | `altium_move_parts`, `altium_route_net`, `altium_autoroute` (Situs), `altium_place_vias`, `altium_apply_pours`, `altium_apply_silkscreen`, `altium_set_design_rules`, `altium_layer_stack`, `altium_find_space` (free spots near a part; overlap check) (**altium-boards**) |+| Mounting holes, fiducials, stitching vias | `altium_board_features {mountingHoles, fiducials, stitching, dryRun}` (**altium-boards**) | | What is selected in Altium; select parts to show the user | `altium_selection {select?}` (**altium-boards**) | | Rotations, channel copies, a precise clearance check | `altium_check_orientation`, `altium_replicate_layout`, `altium_find_space {check, precise}` (**altium-boards**) | | Find a symbol or footprint by name; multi-part symbols; batches | `altium_find_symbol`, `altium_create_symbol {pins with part}`, `{symbols:[..]}` (**altium-libraries**) |

@@ -58,6 +58,8 @@ const CATALOG: &[(&str, &str, &str, &str)] = &[      "The licence (Develop entitlement or a lease) is dead server-side: Altium runs but refuses scripting and can wedge in a modal loop on close. The bridge cannot renew an entitlement - the human renews or re-activates it in the Altium workspace. NOTE: Develop shows NO title licence tail in this state either, so the absent-tail 'Licensed' inference is WRONG while this box is up (measured 2026-09-21)."),     ("license renewal failed", "licence_seat_stranded", "OK",      "Altium could not renew the On-Demand lease. Same cause and fix as 'maximum usage reached': a killed instance is still holding the seat. This dialog RE-FIRES on a timer until the seat is reclaimed, so clearing it is not the fix."),+    ("access violation", "altium_internal", "Send and Close",+     "Altium's crash-report box after an internal fault (an access violation in ScriptingSystem.DLL when a script wrote a pad's mask expansion directly, 2026-10-23). The bridge closes it WITHOUT sending a report. Altium keeps running; the script that faulted stopped part-way: read the document back before trusting what landed."),     ("cannot focus a disabled or invisible window", "altium_internal", "Send and Close",      "Altium's own crash-report dialog, usually raised when a window's state changed while it was focusing a document view. Its only button SENDS a report to Altium — try the title-bar X first if the user's data matters."),     ("unsaved changes", "save_prompt", "",@@ -242,6 +244,12 @@ fn is_licence_chooser(btns: &[String]) -> bool { /// WM_CLOSE on the dialog: the same dismissal its titlebar X performs. Never for any other /// button: closing a question box would silently answer it with its cancel path. pub fn press(hwnd: i64, button: &str) -> Value {+    // Altium's crash-report box (TShowException): its only button SENDS a report to Altium. Close it like its title-bar+    // X instead, which sends nothing (Escape did the same on 2026-10-23).+    if button.eq_ignore_ascii_case("send and close") && crate::win32::post_message_close(hwnd) {+        return json!({"success": true, "clicked": "close (no report sent)", "hwnd": hwnd, "via": "wm_close",+            "note": "Altium's crash-report box was closed without sending a report"});+    }     let r = ab::call("desktop_ui_click", json!({"hwnd": hwnd, "name": button, "role": "button"}), &[], 15);     let ok = r.get("success").and_then(|b| b.as_bool()).unwrap_or(false);     if !ok && button.eq_ignore_ascii_case("ok") && crate::win32::post_message_close(hwnd) {

@@ -4,6 +4,7 @@ //! Installed Libraries, hardened for untrusted zips). use crate::support::{self, s, s_or, timeout_of}; use crate::{ab, agent, shot};+use std::collections::HashMap; use serde_json::{json, Value}; use std::sync::Mutex; use std::time::{Duration, Instant};@@ -64,6 +65,33 @@ pub fn create_footprint(args: &Value) -> Value {     r } +/// The pins argument as the agent's 'des,name,side,offset[,part[,hiddenNet]];...' text. Pins given as objects+/// ({number|designator, name, side, offsetMil?, part?, hiddenNet?}) used to reach the agent as their JSON text and+/// came out as one garbage pin (found 2026-10-23); without an offset they stack down their side 100 mil apart.+pub fn pins_spec(pins: Option<&Value>) -> String {+    match pins {+        Some(Value::Array(a)) => {+            let mut next: HashMap<String, i64> = HashMap::new();+            a.iter().map(|p| {+                let g = |k: &str| p.get(k).map(|v| match v { Value::String(x) => x.clone(), o => o.to_string() }).unwrap_or_default();+                let num = if g("number").is_empty() { g("designator") } else { g("number") };+                let side = if g("side").is_empty() { "left".to_string() } else { g("side").to_lowercase() };+                let off = p.get("offsetMil").or_else(|| p.get("offset")).and_then(|v| v.as_i64().or_else(|| v.as_str().and_then(|x| x.parse().ok())));+                let slot = next.entry(side.clone()).or_insert(100);+                let off = off.unwrap_or(*slot);+                *slot = off + 100;+                let mut f = vec![num, g("name"), side, off.to_string()];+                let (part, hidden) = (g("part"), g("hiddenNet"));+                if !part.is_empty() || !hidden.is_empty() { f.push(if part.is_empty() { "1".into() } else { part }); }+                if !hidden.is_empty() { f.push(hidden); }+                f.iter().map(|x| x.replace([',', ';'], " ")).collect::<Vec<_>>().join(",")+            }).collect::<Vec<_>>().join(";")+        }+        Some(Value::String(x)) => x.clone(),+        _ => String::new(),+    }+}+ pub fn create_symbol(args: &Value) -> Value {     if let Some(g) = support::need_licensed() {         return g;@@ -78,7 +106,7 @@ pub fn create_symbol(args: &Value) -> Value {         &[("name", s_or(args, "name", "")), ("libraryPath", s_or(args, "libraryPath", "")),           ("description", s_or(args, "description", "")), ("designator", s_or(args, "designator", "U")),           ("body_w_mil", s_or(args, "bodyWidthMil", "800")), ("body_h_mil", s_or(args, "bodyHeightMil", "600")),-          ("pins", s_or(args, "pins", ""))],+          ("pins", pins_spec(args.get("pins")))],         None, timeout_of(args, 90));     let mut r = with_shot(r);     if r.get("_hint").is_none() {@@ -1099,3 +1127,15 @@ mod tests {         assert_eq!(sanitise_lib_name("a b/c"), "a_b_c");     } }++#[cfg(test)]+mod pin_tests {+    use super::*;+    #[test]+    fn pin_objects_become_the_agent_spec() {+        let p = json!([{"number": "1", "name": "A", "side": "left"}, {"number": "2", "name": "B", "side": "left"},+                       {"designator": "8", "name": "V+", "side": "right", "offsetMil": 300, "part": 0, "hiddenNet": "VCC"}]);+        assert_eq!(pins_spec(Some(&p)), "1,A,left,100;2,B,left,200;8,V+,right,300,0,VCC");+        assert_eq!(pins_spec(Some(&json!("1,A,left,100"))), "1,A,left,100");+    }+}

@@ -11,6 +11,7 @@ mod design; mod dialogs; mod health; mod install;+mod features; mod inspect; mod instance; mod library;@@ -38,7 +39,7 @@ use tiny_http::{Header, Method, Response, Server}; /// Attached to every failed reply (see the /command handler). const REPORT_ISSUES: &str = "If this looks like an altium-bridge BUG (not a refusal you expected), report it: check for a duplicate with `adom-wiki issue list adom/altium-bridge`, then `adom-wiki issue create adom/altium-bridge --title \"<verb>: <one-line symptom>\" --category bug-report --body \"<what you ran, what you expected, what happened, the VERBATIM response JSON (and errorShot if present), bridgeVersion, the Altium version from altium_status, the OS>\"`. A relay, routing, toast or lifecycle problem belongs on adom/adom-bridge instead. Reports from real machines are how this bridge gets correct: three different Altium builds behaved three different ways in one weekend."; -pub const BRIDGE_VERSION: &str = "0.2.65";+pub const BRIDGE_VERSION: &str = "0.2.66";  fn json_response(status: u16, body: &serde_json::Value) -> Response<std::io::Cursor<Vec<u8>>> {     let data = serde_json::to_vec(body).unwrap_or_else(|_| b"{}".to_vec());

@@ -267,7 +267,7 @@ pub fn routing_state(args: &Value) -> Value {     out } -fn raw(mm: f64) -> i64 {+pub(crate) fn raw(mm: f64) -> i64 {     (mm * PER_MM).round() as i64 } @@ -290,7 +290,7 @@ fn err(code: &str, msg: String, hint: &str) -> Value {  /// Read the live board and check the caller's guard: the right board and the revision it last /// read. A board changed behind the caller's back is refused, never edited blind.-fn guarded(args: &Value) -> Result<Value, Value> {+pub(crate) fn guarded(args: &Value) -> Result<Value, Value> {     let st = routing_state(&json!({"expectPath": args.get("expectPath").cloned().unwrap_or(Value::Null)}));     if st.get("success").and_then(|v| v.as_bool()) != Some(true) {         return Err(st);@@ -310,7 +310,7 @@ fn guarded(args: &Value) -> Result<Value, Value> { }  /// Send one batch to the agent's edit_board and read the board back.-fn apply(ops: &[String], before: &Value, what: &str) -> Value {+pub(crate) fn apply(ops: &[String], before: &Value, what: &str) -> Value {     if ops.is_empty() {         return err("nothing_to_do", format!("{what}: no edits in the request"), "Pass at least one item.");     }

@@ -22,7 +22,7 @@ pub const KNOWN: &[&str] = &[     "list_nets", "net_connections", "layers", "copper_layers", "read_rules",     "set_layer_visibility", "footprint_primitives", "schematic_data", "layer_stack", "net_classes", "diff_pairs", "board_outline", "set_track_width", "find_space", "selection", "check_orientation", "replicate_layout", "outjob_info", "find_symbol", "part_parameters",     // the live-board lane AI Flow drives-    "routing_state", "route_net", "move_parts", "place_vias", "remove_items", "ripup_nets", "apply_pours", "pour_state", "remove_pours", "repour", "routing_drc", "build_board", "set_outline", "set_design_rules", "zoom_to", "add_rule", "build_schematic", "export_manufacturing", "select_net", "silk_state", "apply_silkscreen",+    "routing_state", "route_net", "move_parts", "place_vias", "board_features", "remove_items", "ripup_nets", "apply_pours", "pour_state", "remove_pours", "repour", "routing_drc", "build_board", "set_outline", "set_design_rules", "zoom_to", "add_rule", "build_schematic", "export_manufacturing", "select_net", "silk_state", "apply_silkscreen",     // surfaces     "show_project", "show_schematic", "show_2d_board", "show_3d_board", "show_library",     "show_symbol", "show_footprint", "show_3d_chip", "list_library", "demo",@@ -644,8 +644,8 @@ fn describe() -> Value {             &["sch_connect", "annotate", "update_pcb", "list_library"],             &["Places part 1 of a multi-part component unless partId says otherwise.", "Sheet coordinates are mils from the sheet's lower-left corner; altium_schematic_data shows where the other parts are."],             json!({"sheet": "C:/proj/Main.SchDoc", "library": "C:/proj/Lib.SchLib", "symbol": "TPS54202DDCR", "designator": "U2", "x": 3000, "y": 4000})),-        verb_doc("sch_connect", "Connect pins of placed parts: a wire stub from each pin's outer end plus a net label (kind label), a power port (kind power: GND-like nets get a ground symbol) or the stub alone (kind wire). One undo step.",-            json!({"sheet": "path to the .SchDoc (required)", "connections": "[{designator, pin (number or name), net, kind: label|power|wire (default label), stubMil (default 200)}] (required)", "save": "bool, default true"}),+        verb_doc("sch_connect", "Connect pins of placed parts: a wire stub from each pin's outer end plus a net label (kind label), a power port (kind power: GND-like nets get a ground symbol) or the stub alone (kind wire); or mark a pin left open on purpose with a No ERC marker (kind noerc, no net). One undo step.",+            json!({"sheet": "path to the .SchDoc (required)", "connections": "[{designator, pin (number or name), net, kind: label|power|wire|noerc (default label), stubMil (default 200)}] (required)", "save": "bool, default true"}),             json!({"connected": "int", "results": "[{designator, pin, net, kind, result, endMil}]", "failed": "[..]", "saved": "bool"}), 90,             "Net labels with the same text connect across the project; power ports connect by net name everywhere. Check the result with altium_compile (ERC) or altium_schematic_data.",             &["sch_place_part", "compile", "schematic_data"],@@ -706,6 +706,13 @@ fn describe() -> Value {             &["workspace_search", "sch_place_part", "annotate", "sch_connect", "update_pcb"],             &["Takes 15-70 s. Uses real clicks (double-click the result, click the sheet): Altium comes to the front.", "The part lands near the view's lower-left corner first, then moves to x,y: wires do not follow, so connect it after."],             json!({"sheet": "C:/proj/Main.SchDoc", "query": "100nF 0402 50V", "x": 3000, "y": 2000})),+        verb_doc("board_features", "Add the furniture every real board needs in one undo step: mounting holes (at points or the four corners), fiducials, and a stitching-via grid on a net that keeps clear of every other net's copper, every pad and the board edge.",+            json!({"mountingHoles": "[{x, y, drill?: 3.2, plated?: false, pad?: drill+2.8 when plated, net?}] or {corners: {inset: 4}, drill?, plated?, net?}", "fiducials": "[{x, y, size?: 1, opening?: 2 (mask opening diameter), side?: top|bottom}]", "stitching": "{net (required), pitch?: 5, size?: 0.6, drill?: 0.3, clearance?: 0.3, edge?: 1 (from the outline), region?: [[x,y],..], max?: 400, underParts?: false (vias stay out of each part's pad box)}", "dryRun": "bool - plan only", "filePath": "the .PcbDoc (opened first; expectPath is opened too)", "expectPath": "optional", "expectedRevision": "optional"}),+            json!({"planned": "{mountingHoles, fiducials, stitching:{count, points}}", "applied": "int", "results": "[ok|err:..] per item", "state": "routing_state after"}), 180,+            "dryRun first to see the stitching grid. After stitching, altium_repour so the net's pours join through the vias, then altium_run_drc.",+            &["place_vias", "repour", "run_drc", "routing_state"],+            &["Stitching keeps the pad clearance conservative (a pad's circumscribed circle) and does not look at pours: pours of other nets repour around the vias.", "Unplated holes are bare holes (pad = drill); plated holes take a ring and can join a net (e.g. GND)."],+            json!({"mountingHoles": {"corners": {"inset": 4}, "drill": 3.2}, "fiducials": [{"x": 5, "y": 5}, {"x": 45, "y": 25}], "stitching": {"net": "GND", "pitch": 4}})),         verb_doc("find_space", "Free spots on the board for a part near another (clear of every other part on that side, of that side's tracks and vias, and inside the outline), nearest first; or check:true lists parts that already overlap or leave the outline.",             json!({"near": "designator to place beside (or at: {x, y} mm)", "part": "designator of the part to place (its own size and origin), or sizeMm: [w, h]", "side": "top | bottom (default the part's)", "clearanceMm": "default 0.25", "edgeMm": "from the outline, default 0.3", "count": "default 5", "radiusMm": "search radius, default 10", "copper": "bool, default true - avoid that side's tracks and vias", "check": "bool - report overlaps instead", "precise": "bool, with check - also run Altium's batch DRC and list its Component Clearance violations (primitive to primitive)"}),             json!({"spots": "[{x, y (the part origin, for move_parts), distanceMm, extent}]", "overlaps": "[[a, b]] (check)", "outsideOutline": "[designator] (check)"}), 180,@@ -838,7 +845,7 @@ fn describe() -> Value {             &["errorCode bad_number = a pad field that must be a number was not; nothing is created.", "Units are MILS here; altium_build_footprint specs are millimetres.", "A fresh library carries the stray PCBComponent_1: altium_cleanup_libs."],             json!({"name": "R0603", "libraryPath": "C:/lib/Test.PcbLib", "pads": "1,-30,0,35,37,rect,0;2,30,0,35,37,rect,0"})),         verb_doc("create_symbol", "Create one rectangular symbol from a pin list in a SchLib (the library is created and saved if the path does not exist) and return a proof frame.",-            json!({"name": "string (required)", "libraryPath": "path to a .SchLib (required)", "description": "string", "designator": "string, default 'U'", "bodyWidthMil": "int, default 800", "bodyHeightMil": "int, default 600", "pins": "'des,name,left|right|top|bottom,offset_mil[,part];...' - part 1..N makes a multi-part symbol (a dual op-amp: its A pins part 1, B pins part 2), 0 puts a pin on every part (power)", "symbols": "[{name, pins, ...}] - optional: make several in one call (each over the shared args)", "timeout": "seconds, default 90"}),+            json!({"name": "string (required)", "libraryPath": "path to a .SchLib (required)", "description": "string", "designator": "string, default 'U'", "bodyWidthMil": "int, default 800", "bodyHeightMil": "int, default 600", "pins": "'des,name,left|right|top|bottom,offset_mil[,part[,hiddenNet]];...' - part 1..N makes a multi-part symbol (a dual op-amp: its A pins part 1, B pins part 2), 0 puts a pin on every part (power); hiddenNet hides the pin and joins it to that net by name (shared power pins: '8,V+,left,300,0,VCC', or the compiler reports duplicate pins)", "symbols": "[{name, pins, ...}] - optional: make several in one call (each over the shared args)", "timeout": "seconds, default 90"}),             json!({"data": "{symbol, library, libraryState: opened|created, pins: int}", "shot": "{image: base64 png, width, height}", "windowEtiquette": "background"}), 90,             "Library is UNSAVED: altium_set_params {footprint, params}, then altium_save {filePath: libraryPath}. For multi-mode symbols use altium_build_symbol_modes.",             &["build_symbol_modes", "set_params", "read_symbol", "save"],@@ -1545,6 +1552,7 @@ pub fn dispatch(command: &str, args: &Value, _forwarded: &[(String, String)]) ->         "check_orientation" => crate::design::check_orientation(args),         "replicate_layout" => crate::design::replicate_layout(args),         "outjob_info" => crate::inspect::outjob_info(args),+        "board_features" => crate::features::board_features(args),         "find_symbol" => crate::inspect::find_symbol(args),         "part_parameters" => crate::inspect::part_parameters(args),         "find_space" => crate::design::find_space(args),

@@ -130,8 +130,15 @@ def matrix(w):     M["set_visibility"] = dict(phase=2, **anyo("param visibility", libraryPath=SL, symbolName="TST_SOIC8", param="BatteryParam", visible=False))     M["set_models"] = dict(phase=2, **ok(libraryPath=SL, symbolName="TST_QFN24", footprint="TST_QFN24"))     M["add_models"] = dict(phase=2, **anyo("adds a footprint model row", libraryPath=SL, symbolName="TST_SOIC8", models=[{"type": "PCBLIB", "name": "TST_SOIC8"}]))+    # 0.2.66: pins as objects (they used to arrive as one garbage pin and still pass), a dual op-amp with the shared+    # power pins hidden on their nets; every pin and both parts must arrive     M["create_symbol"] = dict(phase=2, **ok(libraryPath=SL, name="BAT_SYM", designator="U?", description="battery",-                                          pins=[{"number": "1", "name": "A", "side": "left"}, {"number": "2", "name": "B", "side": "right"}]))+                                          pins=[{"number": "1", "name": "OUTA", "side": "right", "part": 1}, {"number": "2", "name": "-INA", "side": "left", "part": 1},+                                                {"number": "3", "name": "+INA", "side": "left", "part": 1}, {"number": "7", "name": "OUTB", "side": "right", "part": 2},+                                                {"number": "6", "name": "-INB", "side": "left", "part": 2}, {"number": "5", "name": "+INB", "side": "left", "part": 2},+                                                {"number": "8", "name": "V+", "side": "left", "offsetMil": 300, "part": 0, "hiddenNet": "VCC"},+                                                {"number": "4", "name": "V-", "side": "left", "offsetMil": 400, "part": 0, "hiddenNet": "GND"}]),+                              check=lambda d: (d.get("data") or {}).get("pins") == 8 and (d.get("data") or {}).get("parts") == 2)     M["clone_symbol"] = dict(phase=2, **ok(libraryPath=SL, **{"from": "BAT_SYM", "to": "BAT_SYM_CLONE"}))     M["rename_symbol"] = dict(phase=2, **ok(libraryPath=SL, **{"from": "BAT_SYM_CLONE", "to": "BAT_SYM_RENAMED"}))     M["remove_symbol"] = dict(phase=2, **ok(libraryPath=SL, symbolName="BAT_SYM_RENAMED"))@@ -246,6 +253,11 @@ def matrix(w):     M["export_manufacturing"] = dict(phase=3.5, timeout=400, **ok(projectPath=LP, pcbPath=LB))     M["outjob_info"] = dict(phase=3.5, **ok(outjobPath=D + "/lane.Manufacturing.OutJob"), check=lambda d: len((d.get("groups") or [{}])[0].get("containers") or []) >= 1)     M["part_parameters"] = dict(phase=3.5, timeout=300, **ok(projectPath=LP), check=lambda d: len(d.get("names") or []) >= 1)+    # 0.2.66: board furniture after the placement checks (the vias would crowd find_space): 2 mm corner holes (under the+    # fab hole rule), one fiducial, at most 4 GND stitching vias; every item must land+    M["board_features"] = dict(phase=3.5, timeout=200, **ok(expectPath=LB, mountingHoles={"corners": {"inset": 2}, "drill": 2.0},+                                                            fiducials=[{"x": 20, "y": 17}], stitching={"net": "GND", "pitch": 5, "max": 4}),+                               check=lambda d: (d.get("applied") or 0) == 9 and d.get("failed") == 0)      # ---- phase 3.5 (0.2.56-0.2.58): BOM and schematic editing on the lane project ----------------     # build_schematic made LP with LS (U1, U2) and LB. A third part goes on the sheet as U?, gets a@@ -257,8 +269,9 @@ def matrix(w):     M["sch_place_part"] = dict(phase=3.5, **ok(sheet=LS, library=SL, symbol="TST_SOIC8", designator="U?", x=8000, y=2000))     M["annotate"] = dict(phase=3.5, timeout=300, **ok(projectPath=LP), check=lambda d: any(r.get("to") == "U3" for r in d.get("renamed") or []))     M["sch_connect"] = dict(phase=3.5, **ok(sheet=LS, connections=[{"designator": "U3", "pin": "1", "net": "N1"},-                                                                    {"designator": "U3", "pin": "4", "net": "GND", "kind": "power"}]),-                            check=lambda d: d.get("connected") == 2)+                                                                    {"designator": "U3", "pin": "4", "net": "GND", "kind": "power"},+                                                                    {"designator": "U3", "pin": "6", "kind": "noerc"}]),+                            check=lambda d: d.get("connected") == 3)     M["sch_edit"] = dict(phase=3.5, **ok(sheet=LS, edits=[{"designator": "U3", "action": "comment", "text": "BATTERY"}]))     M["sch_zoom"] = dict(phase=3.5, **ok(sheet=LS, designators=["U3"], shot=False))     # 0.2.61: swap U1 for the same library part (connections must hold: pins matched by number); the Altium 365

@@ -1,6 +1,6 @@ {   "slug": "altium-bridge",-  "version": "0.2.65",+  "version": "0.2.66",   "type": "app",   "description": "Skills for your container so your AI knows how to drive the Altium Designer bridge (altium_* verbs). The bridge runtime itself is the release zip; Adom Bridge loads that.",   "tags": [

@@ -4,7 +4,7 @@   "type": "app",   "title": "Altium - the Altium Bridge",   "brief": "Adom Bridge for Altium Designer: a resident DelphiScript agent gives the AI eval, the 1,100-command process launcher, all 8 EDA surfaces with screenshots, compile/ERC, DRC, OutJob outputs, native SchLib/PcbLib authoring with STEP 3D bodies, and dialog handling by PID.",-  "version": "0.2.65",+  "version": "0.2.66",   "hero": {     "type": "image",     "path": "screenshots/hero.png"

@@ -172,6 +172,8 @@ ENGINE_HALTING = [     r"\.MinimumRing\b",            # IPCB_MinimumAnnularRing has no MinimumRing on AD 26.11.1 (measured 2026-10-15)     r"\.Priority\s*:=",            # writing a rule's Priority halts with an empty Error box (AD 26.11.1, 2026-10-15);                                    # a newly added rule already lands at priority 1+    r"(?<!PC)\.SolderMaskExpansion\s*:=", r"(?<!PC)\.PasteMaskExpansion\s*:=",  # on a pad: an access violation in+                                   # ScriptingSystem.DLL (AD Develop, 2026-10-23); set them on the pad cache (PC.) instead ]  

@@ -2,8 +2,8 @@ name: altium-boards description: >-   Altium boards through altium-bridge: test boards, shapes, stack-up (planes, 4 layers), net classes,-  diff pairs, track widths, free space for a part, footprint swaps, readback, 2D/3D frames. Use when-  asked for an altium stack-up, net class, where a part fits, or a 3D view.+  diff pairs, track widths, mounting holes, fiducials, stitching vias, free space, footprint swaps,+  readback, 3D. Use when asked for an altium stack-up, net class, mounting holes, where a part fits. ---  Parent skill: **altium-bridge**@@ -145,7 +145,8 @@ All of these need a licensed Altium and read the current document unless a path {layerId, displayed}`; `schematic_data {designator?, pins?, params?}` on the current sheet. They read the CURRENT document: opening a .SchDoc makes board verbs answer "no current PCB board" until a .PcbDoc is opened again — order your calls. Payload is under `data`. Multi-part symbols list-once per part (`partId`).+once per part (`partId`, `partCount`), each with its own pins plus the shared part-0 pins (`part`,+`hidden`, `hiddenNet` on each pin).  `schematic_data` returns an EMPTY `params[]` unless you ask: pass `params:true` (from 0.2.38 — the agent always honoured the flag, but the bridge never sent it, so the field came back empty no matter@@ -236,3 +237,21 @@ altium_net_connections '{"net":"FB"}'                         # airlineMm: each - A move without `rotation` now keeps the part's rotation (it used to turn it to 0). - `footprint_primitives` reports each pad's solder and paste mask expansion (um). +## Mounting holes, fiducials, stitching vias (0.2.66)++```bash+altium_board_features '{"mountingHoles":{"corners":{"inset":4},"drill":3.2},"fiducials":[{"x":5,"y":5},{"x":45,"y":25}],"stitching":{"net":"GND","pitch":4},"dryRun":true}'+altium_board_features '{"mountingHoles":[{"x":10,"y":10,"drill":3.2,"plated":true,"net":"GND"}]}'   # plated, on a net+```++- One undo step, read back. `dryRun:true` returns the plan (every stitching point) without placing anything.+- Mounting holes are unplated bare holes by default (pad = drill); `plated:true` adds a ring (`pad`, default drill+  + 2.8 mm) and can join a net. Fab hole-size rules usually stop below 3.2 mm: the reply's `holeRule` says how to+  widen it (`altium_set_design_rules {hole:{min, max}}`).+- Fiducials are 1 mm copper dots with a 2 mm mask opening and no paste (`size`, `opening`, `side`). Measured: mask+  +0.5 mm, paste -1 mm. The mask is set through the pad cache; writing `Pad.SolderMaskExpansion` crashed Altium+  (an access violation in ScriptingSystem.DLL) and is now refused by the release lint.+- Stitching puts a grid on one net (`pitch`, default 5 mm) inside the outline or `region`, `edge` mm from the edge,+  `clearance` mm from every other net's copper and every pad, out from under parts (their pad box; `underParts:true`+  allows it), and clear of this call's holes and fiducials. Pour the net first: on a board with no pour the vias+  join nothing and DRC reports them as net antennae. Then `altium_repour` and `altium_run_drc`.

@@ -161,8 +161,13 @@ altium_create_footprint '{"libraryPath":"C:\\lib\\Parts.PcbLib","footprints":[{" ```  - A pin's 5th field is its part: 1..N makes a multi-part symbol, and 0 puts the pin on every part (power).-  Measured: part 2 of a dual op-amp, placed with `altium_sch_place_part {partId:2}`, carried OUTB, -INB and +INB-  plus the shared V+ and V-.+  A 6th field hides the pin on that net (`8,V+,left,300,0,VCC`). Do that for shared power pins: visible+  part-0 pins show on every part and the compiler reports "Duplicate pins in component" and duplicate net+  names (measured 2026-10-23, the same with Altium's own placement); hidden on VCC/GND it compiles clean.+- Pins can also be objects: `{number, name, side, offsetMil?, part?, hiddenNet?}`; without an offset they+  stack down their side 100 mil apart.+- Measured (0.2.66): part 2 of a dual op-amp, placed with `altium_sch_place_part {partId:2}`, reads back as+  `partId 2, partCount 2` with OUTB, -INB, +INB and the shared V+/V-. - `find_symbol` puts an exact name first, then the shortest names containing the query. .IntLib files are not   searched; the Altium 365 workspace is searched with `altium_workspace_search`. - `symbols` / `footprints` lists make each item in turn and report each one.

@@ -33,9 +33,12 @@ altium_update_pcb     '{"projectPath":"C:\\proj\\board.PrjPcb","execute":true,"t   (`kind:"label"`), a power port (`kind:"power"`; GND, AGND, VSS... get a ground symbol, other nets a   bar) or nothing (`kind:"wire"`). Pins are matched by number first, then by name. Each connection   answers `ok` or why not (`pin not found on R9`).+- `kind:"noerc"` marks a pin left open on purpose with a No ERC marker on its outer end (no wire, no net):+  `{"designator":"U3","pin":"6","kind":"noerc"}`. A marker off any pin end is reported by compile as+  "Floating No ERC". - `annotate` gives every `R?`, `C?`, `U?` the lowest free number for its prefix across all sheets,-  top-left first. `dryRun:true` shows the plan. Multi-part components with `?` are left to Altium's own-  Tools > Annotation (`skippedMultiPart`).+  top-left first. `dryRun:true` shows the plan. The parts of a multi-part symbol on one sheet share a+  number (U4A + U4B, then U5A + U5B), grouped top-left first, never two of the same part in one group.  ## Parts from the Altium 365 workspace (the shared cloud library) 

@@ -1 +1 @@-0.2.65+0.2.66

@@ -2,7 +2,7 @@   "manifest_version": 1,   "name": "altium",   "displayName": "Altium Designer",-  "version": "0.2.65",+  "version": "0.2.66",   "description": "Drive Altium Designer from Adom: a resident DelphiScript agent (eval + the 1,100-command process launcher), the X2 -R command line, UIA over the VCL shell, dialogs by PID, screenshots of every Altium window, and Altium 365.",   "homepage": "https://wiki.adom.inc/adom/altium-bridge",   "docs": "https://wiki.adom.inc/adom/altium-bridge",@@ -86,6 +86,7 @@     "altium_export_step",     "altium_extension_ping",     "altium_extract_intlib",+    "altium_board_features",     "altium_find_space",     "altium_find_symbol",     "altium_footprint_primitives",@@ -313,6 +314,7 @@       "workspace_search": 180,       "workspace_place": 300,       "find_space": 180,+      "board_features": 180,       "sch_swap_part": 180,       "selection": 60,       "check_orientation": 120,