component
AK7735EQ
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Asahi Kasei Microdevices Audio Interface ICs, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AK7735EQ
Asahi Kasei Microdevices · Audio Interface ICs · LQFP-48(7x7)
AK7735EQ from Asahi Kasei Microdevices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AOUT2R | output | DAC2 Rch analog output; it outputs Hi-Z during power-down, and the pin is supplied from AVDD. |
| 2 | AOUT2L | output | DAC2 Lch analog output; it outputs Hi-Z during power-down, and the pin is supplied from AVDD. |
| 3 | TESTI | input | Test input pin that must be tied low. |
| 4 | LRCK3 | bidirectional | LR channel select clock 3 pin (I/O), referenced to VDD33. |
| 5 | SDOUT4/GPO2 | output | Serial data output 4 pin, or GPO output 2 of DSP2 when selected by DO4SEL; it is pulled down and outputs low in power-down. |
| 6 | BICK3 | bidirectional | Serial bit clock 3 pin (I/O), referenced to VDD33. |
| 7 | SDOUT3/CLKO/GPO1 | output | Serial data output 3 pin, or master clock output (CLKO) or GPO output 1 of DSP1 when selected by DO3SEL; it is pulled down and outputs low in power-down. |
| 8 | SDIN3/JX3 | input | Serial data input 3 pin, or external conditional jump input 3 when selected by DI3SEL; maximum input voltage is the smaller of (VDD33+0.3)V and 4.3V. |
| 9 | SDIN4 | input | Serial data input 4 pin; maximum input voltage is the smaller of (VDD33+0.3)V and 4.3V. |
| 10 | DVSS1 | power_in | Digital ground 1 pin at 0 V; must be connected to the same ground as AVSS and DVSS2/DVSS3. |
| 11 | VDD33 | power_in | Digital I/F power supply pin, 3.0 to 3.6 V (typ. 3.3 V). |
| 12 | XTI | input | Crystal oscillator input pin; connect the crystal between XTI and XTO, or leave open when not used. |
| 13 | XTO | output | Crystal oscillator output pin; connect the crystal between XTI and XTO, or leave open when no crystal is used. |
| 14 | SDIN2/JX0 | input | Serial data input 2 pin, or external conditional jump input 0 when selected by DI2SEL; referenced to TVDD. |
| 15 | LRCK2/JX1 | bidirectional | LR channel select clock 2 pin (I/O), or external conditional jump input 1 when selected by LCK2SEL (requires MSN2 = 0); referenced to TVDD. |
| 16 | BICK2/JX2 | bidirectional | Serial bit clock 2 pin (I/O), or external conditional jump input 2 when selected by BCK2SEL (requires MSN2 = 0); referenced to TVDD. |
| 17 | SDIN1 | input | Serial data input 1 pin; referenced to TVDD. |
| 18 | LRCK1 | bidirectional | LR channel select clock 1 pin (I/O); referenced to TVDD. |
| 19 | BICK1 | bidirectional | Serial bit clock 1 pin (I/O); referenced to TVDD. |
| 20 | SDOUT1/RDY | output | Serial data output 1 pin, or RDY signal output when selected by DO1SEL; it is pulled down and outputs low in power-down. |
| 21 | TVDD | power_in | Digital I/F power supply pin, 1.7 to 3.6 V (typ. 3.3 V). |
| 22 | DVSS2 | power_in | Digital ground 2 pin at 0 V; must be connected to the same ground as the other ground pins. |
| 23 | STO/RDY/SDOUT2 | output | Status output pin (STO, output low in power-down), or RDY signal output, or SDOUT2 serial data output depending on DO2SEL; it is pulled down in power-down. |
| 24 | CSN | input | SPI chip select pin, to be held high during power-down or when SPI is not used; in I2C mode it is the chip address pin and must be pulled up or pulled down. |
| 25 | SO/SDA | bidirectional | Serial data output pin for SPI (must be pulled up or down in SPI mode, Hi-Z in power-down), or serial data I/O for I2C; referenced to TVDD. |
| 26 | SCLK/SCL | input | Serial data clock input pin for SPI, or serial clock input for I2C; referenced to TVDD. |
| 27 | SI/I2CFIL | input | Serial data input pin for SPI, or I2C mode select input in I2C mode (L = Fast Mode 400 kHz, H = Fast Mode Plus 1 MHz, which should be fixed to TVDD2 as printed); referenced to TVDD. |
| 28 | PDN | input | Power-down pin that must be held low while power is supplied and may be set high only after all power supplies are applied and settled; referenced to TVDD. |
| 29 | AVDRV | output | VREG output pin; connect a 2.2 uF (±30%) ceramic capacitor between this pin and DVSS3, and do not connect it to an external circuit. |
| 30 | DVSS3 | power_in | Digital ground 3 pin at 0 V; must be connected to the same ground as the other ground pins. |
| 31 | LVDD | power_in | Digital core power supply pin, 3.0 to 3.6 V (typ. 3.3 V). |
| 32 | AIN2RN/AIN4R | input | ADC2 Rch inverted differential input 2, or ADC2 Rch single-ended input 4; referenced to AVDD. |
| 33 | AIN2RP/AIN3R | input | ADC2 Rch non-inverted differential input 2, or ADC2 Rch single-ended input 3; referenced to AVDD. |
| 34 | AIN2LN/AIN4L | input | ADC2 Lch inverted differential input 2, or ADC2 Lch single-ended input 4; referenced to AVDD. |
| 35 | AIN2LP/AIN3L | input | ADC2 Lch non-inverted differential input 2, or ADC2 Lch single-ended input 3; referenced to AVDD. |
| 36 | INN2 | input | ADC1 Rch inverted differential input 2; referenced to AVDD. |
| 37 | AIN1R/INP2 | input | ADC1 Rch single-ended input 1, or ADC1 Rch non-inverted differential input 2; referenced to AVDD. |
| 38 | INN1 | input | ADC1 Lch inverted differential input 1; referenced to AVDD. |
| 39 | AIN1L/INP1 | input | ADC1 Lch single-ended input 1, or ADC1 Lch non-inverted differential input 1; referenced to AVDD. |
| 40 | MPREF | output | Ripple filter pin for the microphone power supply; connect a 1 uF ceramic capacitor between this pin and AVSS, and do not connect it to an external circuit. |
| 41 | MPWR | output | Power supply output pin for the microphone, which outputs Hi-Z during power-down. |
| 42 | AVDD | power_in | Analog power supply pin, 3.0 to 3.6 V (typ. 3.3 V). |
| 43 | AVSS | power_in | Analog ground pin at 0 V; must be connected to the same ground as DVSS1/DVSS2/DVSS3. |
| 44 | VCOM | output | Analog common voltage output pin (AVDD/2); connect a 2.2 uF ceramic capacitor between this pin and AVSS, do not connect it to an external circuit, and it outputs low in power-down. |
| 45 | VREFH | input | Analog high-level reference voltage input pin that must be connected to AVDD. |
| 46 | VREFL | input | Analog low-level reference voltage input pin that must be connected to AVSS. |
| 47 | AOUT1R | output | DAC1 Rch analog output pin, which outputs Hi-Z during power-down. |
| 48 | AOUT1L | output | DAC1 Lch analog output pin, which outputs Hi-Z during power-down. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | LQFP-48(7x7) |
| Category | Interface ICs |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage (absolute max) | AVDD | -0.3 | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 | |
| Digital1 (Core) Supply Voltage (absolute max) | LVDD | -0.3 | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 | |
| Digital2 (I/F) Supply Voltage (absolute max) | TVDD | -0.3 | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 | |
| Digital3 (I/F) Supply Voltage (absolute max) | VDD33 | -0.3 | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 | |
| Difference between grounds (AVSS, DVSS1, DVSS2, DVSS3) (absolute max) | ΔGND | -0.3 | 0.3 | V | 13 | ||
| Input Current (except power supply pins) (absolute max) | IIN | -10 | 10 | mA | except power supply pins | 13 | |
| Analog Input Voltage (absolute max) | VINA | -0.3 | V | max = smaller of (AVDD+0.3) and 4.3 (note 4) | 13 | ||
| Digital Input Voltage, TVDD group (absolute max) | VIND1 | -0.3 | V | max = smaller of (TVDD+0.3) and 4.3 (note 5) | 13 | ||
| Digital Input Voltage, VDD33 group (absolute max) | VIND2 | -0.3 | V | max = smaller of (VDD33+0.3) and 4.3 (note 6) | 13 | ||
| Ambient Temperature (AK7735EQ) (absolute max) | Ta | -20 | 85 | °C | AK7735EQ | 13 | |
| Storage Temperature (absolute max) | Tstg | -65 | 150 | °C | 13 | ||
| Analog Supply Voltage (recommended) | AVDD | 3 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital1 (Core) Supply Voltage (recommended) | LVDD | 3 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital2 (I/F) Supply Voltage (recommended) | TVDD | 1.7 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital3 (I/F) Supply Voltage (recommended) | VDD33 | 3 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Difference AVDD, LVDD (recommended) | AVDD, LVDD | -0.1 | 0 | 0.1 | V | 13 | |
| Difference AVDD, VDD33 (recommended) | AVDD, VDD33 | -0.1 | 0 | 0.1 | V | 13 | |
| Difference LVDD, VDD33 (recommended) | LVDD, VDD33 | -0.1 | 0 | 0.1 | V | 13 | |
| Difference LVDD, TVDD (recommended) | LVDD, TVDD | -0.1 | 0.1 | V | 13 | ||
| MIC AMP Input Impedance | 14 | 20 | 26 | kΩ | Ta=25°C; AVDD=LVDD=TVDD=VDD33=3.3V | 14 | |
| MIC AMP Gain | -1 | 0 | 1 | dB | MGNL[3:0]bits=0h, MGNR[3:0]bits=0h | 14 | |
| MIC AMP Gain | 1 | 2 | 3 | dB | MGNL[3:0]bits=1h, MGNR[3:0]bits=1h | 14 | |
| MIC AMP Gain | 3 | 4 | 5 | dB | MGNL[3:0]bits=2h, MGNR[3:0]bits=2h | 14 | |
| MIC AMP Gain | 5 | 6 | 7 | dB | MGNL[3:0]bits=3h, MGNR[3:0]bits=3h | 14 | |
| MIC AMP Gain | 7 | 8 | 9 | dB | MGNL[3:0]bits=4h, MGNR[3:0]bits=4h | 14 | |
| MIC AMP Gain | 9 | 10 | 11 | dB | MGNL[3:0]bits=5h, MGNR[3:0]bits=5h | 14 | |
| MIC AMP Gain | 11 | 12 | 13 | dB | MGNL[3:0]bits=6h, MGNR[3:0]bits=6h | 14 | |
| MIC AMP Gain | 13 | 14 | 15 | dB | MGNL[3:0]bits=7h, MGNR[3:0]bits=7h | 14 | |
| MIC AMP Gain | 15 | 16 | 17 | dB | MGNL[3:0]bits=8h, MGNR[3:0]bits=8h | 14 | |
| MIC AMP Gain | 17 | 18 | 19 | dB | MGNL[3:0]bits=9h, MGNR[3:0]bits=9h | 14 | |
| MIC AMP Gain | 20 | 21 | 22 | dB | MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah | 14 | |
| MIC AMP Gain | 23 | 24 | 25 | dB | MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh | 14 | |
| MIC AMP Gain | 26 | 27 | 28 | dB | MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch | 14 | |
| MIC AMP Gain | 29 | 30 | 31 | dB | MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh | 14 | |
| MIC AMP Gain | 32 | 33 | 34 | dB | MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh | 14 | |
| MIC AMP Gain | 35 | 36 | 37 | dB | MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh | 14 | |
| MIC Bias Output Voltage | 2.3 | 2.5 | 2.7 | V | Ta=25°C; AVDD=LVDD=TVDD=VDD33=3.3V; Measurement Frequency=20Hz~20kHz | 14 | |
| Input Full Scale Voltage, Differential Input (note 13: ADC1VL/R=0, MGNL/R=0h) | 2.1 | 2.3 | 2.5 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=0h (0dB) | 15 | |
| Input Full Scale Voltage, Differential Input (note 14: ADC1VL/R=0, MGNL/R=9h) | 0.264 | 0.29 | 0.315 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=9h (+18dB) | 15 | |
| Input Full Scale Voltage, Differential Input (note 15: ADC1VL/R=1, MGNL/R=0h) | 2.55 | 2.83 | 3.11 | Vpp | ADC1VL/R bits=1; MGNL/R[3:0] bits=0h (0dB) | 15 | |
| Input Full Scale Voltage, Single-ended Input (note 13: ADC1VL/R=0, MGNL/R=0h) | 2.1 | 2.3 | 2.5 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=0h (0dB) | 15 | |
| Input Full Scale Voltage, Single-ended Input (note 14: ADC1VL/R=0, MGNL/R=9h) | 0.264 | 0.29 | 0.315 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=9h (+18dB) | 15 | |
| Input Full Scale Voltage, Single-ended Input (note 15: ADC1VL/R=1, MGNL/R=0h) | 2.55 | 2.83 | 3.11 | Vpp | ADC1VL/R bits=1; MGNL/R[3:0] bits=0h (0dB) | 15 | |
| Power-Up Current, AVDD | AVDD | 23 | 33 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 | |
| Power-Up Current, LVDD | LVDD | 55 | 98 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 | |
| Power-Up Current, TVDD | TVDD | 4 | 6 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 | |
| Power-Up Current, VDD33 | VDD33 | 5 | 8 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 | |
| Digital Filter + SCF + SMF Frequency Response | -0.3 | 0.1 | dB | fs=48kHz; 0~20.0kHz | 24 | ||
| Digital Filter + SCF + SMF Frequency Response | -0.5 | 0.1 | dB | fs=96kHz; 0~40.0kHz | 24 | ||
| Digital Filter + SCF + SMF Frequency Response | -1.9 | 0.1 | dB | fs=192kHz; 0~80.0kHz | 24 | ||
| Low-Level Output Voltage, SDOUT1/RDY, STO/RDY/SDOUT2, SO/SDA (VOL1) | VOL1 | 0.3 | V | Iout=100µA | 30 | ||
| Low-Level Output Voltage, SDOUT3/CLKO/GPO1, SDOUT4/GPO2 (VOL2) | VOL2 | 0.3 | V | Iout=100µA | 30 | ||
| SDA Low-Level Output Voltage, Fast Mode (VOL3) | VOL3 | 0.4 | V | Fast Mode; TVDD ≥ 2.0V; Iout=3mA | 30 | ||
| SDA Low-Level Output Voltage, Fast Mode Plus (VOL3) | VOL3 | 0.4 | V | Fast Mode Plus; TVDD ≥ 2.0V; Iout=20mA | 30 | ||
| Input Leak Current | Iin | -10 | 10 | µA | Except internal pulled-down pins and XTI pin | 30 | |
| XTI Clock Input Duty Cycle | 40 | 50 | 60 | % | XTI clock input | 31 | |
| XTI Clock Input Frequency | fXTI | 0.256 | 24.576 | MHz | XTI clock input | 31 | |
| LRCK Input Frequency (Slave Mode) | fs | 8 | 192 | kHz | Slave mode | 31 | |
| BICK Input Frequency (Slave Mode) | fBCLK | 0.256 | 24.576 | MHz | Slave mode; fBCLK ≥ 2 x fs x (Input/Output Data Length) (note 43) | 31 | |
| PDN Pulse Width | tRST | 600 | ns | Reset timing (Figure 3) | 31 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | Lead frame: Copper | 139 |
CAD (KiCad official)
- Symbol:
AK7735EQ - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
ak7735eq-etched.step/ak7735eq-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ak7735eq.step/ak7735eq.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Asahi Kasei Microdevices datasheet (142 pp, sha256
2ca2c4f05a8540c6, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AK7735EQ
**Asahi Kasei Microdevices** · Audio Interface ICs · LQFP-48(7x7)
AK7735EQ from Asahi Kasei Microdevices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AOUT2R | output | DAC2 Rch analog output; it outputs Hi-Z during power-down, and the pin is supplied from AVDD. |
| 2 | AOUT2L | output | DAC2 Lch analog output; it outputs Hi-Z during power-down, and the pin is supplied from AVDD. |
| 3 | TESTI | input | Test input pin that must be tied low. |
| 4 | LRCK3 | bidirectional | LR channel select clock 3 pin (I/O), referenced to VDD33. |
| 5 | SDOUT4/GPO2 | output | Serial data output 4 pin, or GPO output 2 of DSP2 when selected by DO4SEL; it is pulled down and outputs low in power-down. |
| 6 | BICK3 | bidirectional | Serial bit clock 3 pin (I/O), referenced to VDD33. |
| 7 | SDOUT3/CLKO/GPO1 | output | Serial data output 3 pin, or master clock output (CLKO) or GPO output 1 of DSP1 when selected by DO3SEL; it is pulled down and outputs low in power-down. |
| 8 | SDIN3/JX3 | input | Serial data input 3 pin, or external conditional jump input 3 when selected by DI3SEL; maximum input voltage is the smaller of (VDD33+0.3)V and 4.3V. |
| 9 | SDIN4 | input | Serial data input 4 pin; maximum input voltage is the smaller of (VDD33+0.3)V and 4.3V. |
| 10 | DVSS1 | power_in | Digital ground 1 pin at 0 V; must be connected to the same ground as AVSS and DVSS2/DVSS3. |
| 11 | VDD33 | power_in | Digital I/F power supply pin, 3.0 to 3.6 V (typ. 3.3 V). |
| 12 | XTI | input | Crystal oscillator input pin; connect the crystal between XTI and XTO, or leave open when not used. |
| 13 | XTO | output | Crystal oscillator output pin; connect the crystal between XTI and XTO, or leave open when no crystal is used. |
| 14 | SDIN2/JX0 | input | Serial data input 2 pin, or external conditional jump input 0 when selected by DI2SEL; referenced to TVDD. |
| 15 | LRCK2/JX1 | bidirectional | LR channel select clock 2 pin (I/O), or external conditional jump input 1 when selected by LCK2SEL (requires MSN2 = 0); referenced to TVDD. |
| 16 | BICK2/JX2 | bidirectional | Serial bit clock 2 pin (I/O), or external conditional jump input 2 when selected by BCK2SEL (requires MSN2 = 0); referenced to TVDD. |
| 17 | SDIN1 | input | Serial data input 1 pin; referenced to TVDD. |
| 18 | LRCK1 | bidirectional | LR channel select clock 1 pin (I/O); referenced to TVDD. |
| 19 | BICK1 | bidirectional | Serial bit clock 1 pin (I/O); referenced to TVDD. |
| 20 | SDOUT1/RDY | output | Serial data output 1 pin, or RDY signal output when selected by DO1SEL; it is pulled down and outputs low in power-down. |
| 21 | TVDD | power_in | Digital I/F power supply pin, 1.7 to 3.6 V (typ. 3.3 V). |
| 22 | DVSS2 | power_in | Digital ground 2 pin at 0 V; must be connected to the same ground as the other ground pins. |
| 23 | STO/RDY/SDOUT2 | output | Status output pin (STO, output low in power-down), or RDY signal output, or SDOUT2 serial data output depending on DO2SEL; it is pulled down in power-down. |
| 24 | CSN | input | SPI chip select pin, to be held high during power-down or when SPI is not used; in I2C mode it is the chip address pin and must be pulled up or pulled down. |
| 25 | SO/SDA | bidirectional | Serial data output pin for SPI (must be pulled up or down in SPI mode, Hi-Z in power-down), or serial data I/O for I2C; referenced to TVDD. |
| 26 | SCLK/SCL | input | Serial data clock input pin for SPI, or serial clock input for I2C; referenced to TVDD. |
| 27 | SI/I2CFIL | input | Serial data input pin for SPI, or I2C mode select input in I2C mode (L = Fast Mode 400 kHz, H = Fast Mode Plus 1 MHz, which should be fixed to TVDD2 as printed); referenced to TVDD. |
| 28 | PDN | input | Power-down pin that must be held low while power is supplied and may be set high only after all power supplies are applied and settled; referenced to TVDD. |
| 29 | AVDRV | output | VREG output pin; connect a 2.2 uF (±30%) ceramic capacitor between this pin and DVSS3, and do not connect it to an external circuit. |
| 30 | DVSS3 | power_in | Digital ground 3 pin at 0 V; must be connected to the same ground as the other ground pins. |
| 31 | LVDD | power_in | Digital core power supply pin, 3.0 to 3.6 V (typ. 3.3 V). |
| 32 | AIN2RN/AIN4R | input | ADC2 Rch inverted differential input 2, or ADC2 Rch single-ended input 4; referenced to AVDD. |
| 33 | AIN2RP/AIN3R | input | ADC2 Rch non-inverted differential input 2, or ADC2 Rch single-ended input 3; referenced to AVDD. |
| 34 | AIN2LN/AIN4L | input | ADC2 Lch inverted differential input 2, or ADC2 Lch single-ended input 4; referenced to AVDD. |
| 35 | AIN2LP/AIN3L | input | ADC2 Lch non-inverted differential input 2, or ADC2 Lch single-ended input 3; referenced to AVDD. |
| 36 | INN2 | input | ADC1 Rch inverted differential input 2; referenced to AVDD. |
| 37 | AIN1R/INP2 | input | ADC1 Rch single-ended input 1, or ADC1 Rch non-inverted differential input 2; referenced to AVDD. |
| 38 | INN1 | input | ADC1 Lch inverted differential input 1; referenced to AVDD. |
| 39 | AIN1L/INP1 | input | ADC1 Lch single-ended input 1, or ADC1 Lch non-inverted differential input 1; referenced to AVDD. |
| 40 | MPREF | output | Ripple filter pin for the microphone power supply; connect a 1 uF ceramic capacitor between this pin and AVSS, and do not connect it to an external circuit. |
| 41 | MPWR | output | Power supply output pin for the microphone, which outputs Hi-Z during power-down. |
| 42 | AVDD | power_in | Analog power supply pin, 3.0 to 3.6 V (typ. 3.3 V). |
| 43 | AVSS | power_in | Analog ground pin at 0 V; must be connected to the same ground as DVSS1/DVSS2/DVSS3. |
| 44 | VCOM | output | Analog common voltage output pin (AVDD/2); connect a 2.2 uF ceramic capacitor between this pin and AVSS, do not connect it to an external circuit, and it outputs low in power-down. |
| 45 | VREFH | input | Analog high-level reference voltage input pin that must be connected to AVDD. |
| 46 | VREFL | input | Analog low-level reference voltage input pin that must be connected to AVSS. |
| 47 | AOUT1R | output | DAC1 Rch analog output pin, which outputs Hi-Z during power-down. |
| 48 | AOUT1L | output | DAC1 Lch analog output pin, which outputs Hi-Z during power-down. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | LQFP-48(7x7) |
| Category | Interface ICs |
| Pins | 48 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Supply Voltage (absolute max) | AVDD | -0.3 | | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital1 (Core) Supply Voltage (absolute max) | LVDD | -0.3 | | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital2 (I/F) Supply Voltage (absolute max) | TVDD | -0.3 | | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital3 (I/F) Supply Voltage (absolute max) | VDD33 | -0.3 | | 4.3 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Difference between grounds (AVSS, DVSS1, DVSS2, DVSS3) (absolute max) | ΔGND | -0.3 | | 0.3 | V | | 13 |
| Input Current (except power supply pins) (absolute max) | IIN | -10 | | 10 | mA | except power supply pins | 13 |
| Analog Input Voltage (absolute max) | VINA | -0.3 | | | V | max = smaller of (AVDD+0.3) and 4.3 (note 4) | 13 |
| Digital Input Voltage, TVDD group (absolute max) | VIND1 | -0.3 | | | V | max = smaller of (TVDD+0.3) and 4.3 (note 5) | 13 |
| Digital Input Voltage, VDD33 group (absolute max) | VIND2 | -0.3 | | | V | max = smaller of (VDD33+0.3) and 4.3 (note 6) | 13 |
| Ambient Temperature (AK7735EQ) (absolute max) | Ta | -20 | | 85 | °C | AK7735EQ | 13 |
| Storage Temperature (absolute max) | Tstg | -65 | | 150 | °C | | 13 |
| Analog Supply Voltage (recommended) | AVDD | 3 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital1 (Core) Supply Voltage (recommended) | LVDD | 3 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital2 (I/F) Supply Voltage (recommended) | TVDD | 1.7 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Digital3 (I/F) Supply Voltage (recommended) | VDD33 | 3 | 3.3 | 3.6 | V | AVSS=DVSS1=DVSS2=DVSS3=0V | 13 |
| Difference AVDD, LVDD (recommended) | AVDD, LVDD | -0.1 | 0 | 0.1 | V | | 13 |
| Difference AVDD, VDD33 (recommended) | AVDD, VDD33 | -0.1 | 0 | 0.1 | V | | 13 |
| Difference LVDD, VDD33 (recommended) | LVDD, VDD33 | -0.1 | 0 | 0.1 | V | | 13 |
| Difference LVDD, TVDD (recommended) | LVDD, TVDD | -0.1 | | 0.1 | V | | 13 |
| MIC AMP Input Impedance | | 14 | 20 | 26 | kΩ | Ta=25°C; AVDD=LVDD=TVDD=VDD33=3.3V | 14 |
| MIC AMP Gain | | -1 | 0 | 1 | dB | MGNL[3:0]bits=0h, MGNR[3:0]bits=0h | 14 |
| MIC AMP Gain | | 1 | 2 | 3 | dB | MGNL[3:0]bits=1h, MGNR[3:0]bits=1h | 14 |
| MIC AMP Gain | | 3 | 4 | 5 | dB | MGNL[3:0]bits=2h, MGNR[3:0]bits=2h | 14 |
| MIC AMP Gain | | 5 | 6 | 7 | dB | MGNL[3:0]bits=3h, MGNR[3:0]bits=3h | 14 |
| MIC AMP Gain | | 7 | 8 | 9 | dB | MGNL[3:0]bits=4h, MGNR[3:0]bits=4h | 14 |
| MIC AMP Gain | | 9 | 10 | 11 | dB | MGNL[3:0]bits=5h, MGNR[3:0]bits=5h | 14 |
| MIC AMP Gain | | 11 | 12 | 13 | dB | MGNL[3:0]bits=6h, MGNR[3:0]bits=6h | 14 |
| MIC AMP Gain | | 13 | 14 | 15 | dB | MGNL[3:0]bits=7h, MGNR[3:0]bits=7h | 14 |
| MIC AMP Gain | | 15 | 16 | 17 | dB | MGNL[3:0]bits=8h, MGNR[3:0]bits=8h | 14 |
| MIC AMP Gain | | 17 | 18 | 19 | dB | MGNL[3:0]bits=9h, MGNR[3:0]bits=9h | 14 |
| MIC AMP Gain | | 20 | 21 | 22 | dB | MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah | 14 |
| MIC AMP Gain | | 23 | 24 | 25 | dB | MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh | 14 |
| MIC AMP Gain | | 26 | 27 | 28 | dB | MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch | 14 |
| MIC AMP Gain | | 29 | 30 | 31 | dB | MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh | 14 |
| MIC AMP Gain | | 32 | 33 | 34 | dB | MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh | 14 |
| MIC AMP Gain | | 35 | 36 | 37 | dB | MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh | 14 |
| MIC Bias Output Voltage | | 2.3 | 2.5 | 2.7 | V | Ta=25°C; AVDD=LVDD=TVDD=VDD33=3.3V; Measurement Frequency=20Hz~20kHz | 14 |
| Input Full Scale Voltage, Differential Input (note 13: ADC1VL/R=0, MGNL/R=0h) | | 2.1 | 2.3 | 2.5 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=0h (0dB) | 15 |
| Input Full Scale Voltage, Differential Input (note 14: ADC1VL/R=0, MGNL/R=9h) | | 0.264 | 0.29 | 0.315 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=9h (+18dB) | 15 |
| Input Full Scale Voltage, Differential Input (note 15: ADC1VL/R=1, MGNL/R=0h) | | 2.55 | 2.83 | 3.11 | Vpp | ADC1VL/R bits=1; MGNL/R[3:0] bits=0h (0dB) | 15 |
| Input Full Scale Voltage, Single-ended Input (note 13: ADC1VL/R=0, MGNL/R=0h) | | 2.1 | 2.3 | 2.5 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=0h (0dB) | 15 |
| Input Full Scale Voltage, Single-ended Input (note 14: ADC1VL/R=0, MGNL/R=9h) | | 0.264 | 0.29 | 0.315 | Vpp | ADC1VL/R bits=0; MGNL/R[3:0] bits=9h (+18dB) | 15 |
| Input Full Scale Voltage, Single-ended Input (note 15: ADC1VL/R=1, MGNL/R=0h) | | 2.55 | 2.83 | 3.11 | Vpp | ADC1VL/R bits=1; MGNL/R[3:0] bits=0h (0dB) | 15 |
| Power-Up Current, AVDD | AVDD | | 23 | 33 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 |
| Power-Up Current, LVDD | LVDD | | 55 | 98 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 |
| Power-Up Current, TVDD | TVDD | | 4 | 6 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 |
| Power-Up Current, VDD33 | VDD33 | | 5 | 8 | mA | PDN=H; fs=192kHz; BICK=64fs; Master Mode; CL=20pF | 19 |
| Digital Filter + SCF + SMF Frequency Response | | -0.3 | | 0.1 | dB | fs=48kHz; 0~20.0kHz | 24 |
| Digital Filter + SCF + SMF Frequency Response | | -0.5 | | 0.1 | dB | fs=96kHz; 0~40.0kHz | 24 |
| Digital Filter + SCF + SMF Frequency Response | | -1.9 | | 0.1 | dB | fs=192kHz; 0~80.0kHz | 24 |
| Low-Level Output Voltage, SDOUT1/RDY, STO/RDY/SDOUT2, SO/SDA (VOL1) | VOL1 | | | 0.3 | V | Iout=100µA | 30 |
| Low-Level Output Voltage, SDOUT3/CLKO/GPO1, SDOUT4/GPO2 (VOL2) | VOL2 | | | 0.3 | V | Iout=100µA | 30 |
| SDA Low-Level Output Voltage, Fast Mode (VOL3) | VOL3 | | | 0.4 | V | Fast Mode; TVDD ≥ 2.0V; Iout=3mA | 30 |
| SDA Low-Level Output Voltage, Fast Mode Plus (VOL3) | VOL3 | | | 0.4 | V | Fast Mode Plus; TVDD ≥ 2.0V; Iout=20mA | 30 |
| Input Leak Current | Iin | -10 | | 10 | µA | Except internal pulled-down pins and XTI pin | 30 |
| XTI Clock Input Duty Cycle | | 40 | 50 | 60 | % | XTI clock input | 31 |
| XTI Clock Input Frequency | fXTI | 0.256 | | 24.576 | MHz | XTI clock input | 31 |
| LRCK Input Frequency (Slave Mode) | fs | 8 | | 192 | kHz | Slave mode | 31 |
| BICK Input Frequency (Slave Mode) | fBCLK | 0.256 | | 24.576 | MHz | Slave mode; fBCLK ≥ 2 x fs x (Input/Output Data Length) (note 43) | 31 |
| PDN Pulse Width | tRST | 600 | | | ns | Reset timing (Figure 3) | 31 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | Copper | | Lead frame: Copper | 139 |
## CAD (KiCad official)
- Symbol: `AK7735EQ`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `ak7735eq-etched.step` / `ak7735eq-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ak7735eq.step` / `ak7735eq.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Asahi Kasei Microdevices datasheet](docs/ak7735eq-datasheet.pdf) (142 pp, sha256 `2ca2c4f05a8540c6`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ak7735eq-datasheet.pdf)