component
AK5552VN
Public Made by Adomby adom
Asahi Kasei Microdevices Digital To Analog Converters (DACs), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAK5552VN
Asahi Kasei Microdevices · Digital To Analog Converters (DACs) · QFN-48-EP(7x7)
AK5552VN from Asahi Kasei Microdevices, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal bonding; connect to AVSS. |
| 2 | VREFL1 | input | ADC low-level voltage reference input; must be connected to AVSS. |
| 3 | VREFH1 | input | ADC high-level voltage reference input; must not exceed AVDD+0.1 V and is specified at 4.5-5.5 V. |
| 4 | AIN2N | input | Channel 2 negative analog input pin. |
| 5 | AIN2P | input | Channel 2 positive analog input pin. |
| 6 | AVDD | power_in | Analog power supply for AIN1-2, 4.5-5.5 V. |
| 7 | AVSS | power_in | Analog ground for AIN1-2. |
| 8 | TESTIN1 | passive | Test input pin 1; the datasheet gives no operating function for this pin. |
| 9 | TESTIN2 | passive | Test input pin 2; the datasheet gives no operating function for this pin. |
| 10 | TESTIN3 | passive | Test input pin 3; the datasheet gives no operating function for this pin. |
| 11 | TESTIN4 | passive | Test input pin 4; the datasheet gives no operating function for this pin. |
| 12 | NC | unconnected | No internal bonding; connect to AVSS. |
| 13 | TESTIN5 | passive | Test input pin 5; the datasheet gives no operating function for this pin. |
| 14 | TESTIN6 | passive | Test input pin 6; the datasheet gives no operating function for this pin. |
| 15 | TEST | input | TEST enable pin. |
| 16 | MCLK | input | Master clock input pin. |
| 17 | TVDD | power_in | Digital I/O buffer and LDO power supply, 1.7-1.98 V when LDOE is L or 3.0-3.6 V when LDOE is H. |
| 18 | DVSS | power_in | Digital ground pin; DVSS and AVSS must be connected to the same analog ground plane. |
| 19 | VDD18 | power_in | Digital core power supply, 1.7-1.98 V when LDOE is L; when LDOE is H this pin is the LDO stabilization capacitor connection and cannot supply external circuits. |
| 20 | PDN | input | Reset and power-down pin: L resets and powers down the device, H is normal operation. |
| 21 | PW0 | input | Power management pin and channel summation select pin 1. |
| 22 | PW1 | input | Power management pin and channel summation select pin 2. |
| 23 | PW2 | input | Power management pin and channel summation select pin 3. |
| 24 | MSN | input | Master/slave select pin. |
| 25 | BICK/DCLK | bidirectional | BICK is the audio serial data clock input in PCM slave mode and output in PCM master mode; DCLK is the DSD clock output in DSD mode; pin is pulled down by 100 kΩ internally. |
| 26 | LRCK/DSDOL1 | bidirectional | LRCK is the channel clock input in PCM slave mode and output in PCM master mode; DSDOL1 is the AIN1 serial data output in DSD mode; pin is pulled down by 100 kΩ internally. |
| 27 | TDMIN/DSDOR1 | bidirectional | TDMIN is the TDM data input in PCM mode; DSDOR1 is the AIN2 serial data output in DSD mode; pin is pulled down by 100 kΩ internally. |
| 28 | SDTO1 | output | Audio serial data output for AIN1 and AIN2 in PCM mode; output is L when powered down. |
| 29 | TESTO1 | output | Test output pin 1; high-impedance when powered down. |
| 30 | OVF | output | Analog input overflow flag output; goes H when an analog input overflows (more than -0.3 dBFS) and is L when powered down. |
| 31 | CKS0/SDA/CDTI | bidirectional | CKS0 is the clock mode select input; SDA is the I2C control data I/O (high-impedance when powered down); CDTI is the control data input in 3-wire mode. |
| 32 | CKS1/CAD0_I2C/CSN | input | CKS1 is the clock mode select input; CAD0_I2C is the I2C chip address 0 pin; CSN is the 3-wire chip select input. |
| 33 | CKS2/SCL/CCLK | input | CKS2 is the clock mode select input; SCL is the I2C control clock pin; CCLK is the 3-wire control clock input. |
| 34 | CKS3/CAD1 | input | CKS3 is the clock mode select input; CAD1 is the chip address 1 pin in I2C or 3-wire control mode. |
| 35 | SLOW/DCKB | input | SLOW selects the slow roll-off digital filter in PCM mode; DCKB sets the DCLK polarity in DSD mode. |
| 36 | SD/PMOD | input | SD selects the short-delay digital filter in PCM mode; PMOD selects the DSD phase modulation mode. |
| 37 | DIF0/DSDSEL0 | input | DIF0 selects the PCM audio format (L: MSB justified, H: I2S); DSDSEL0 controls the DSD sampling rate. |
| 38 | DIF1/DSDSEL1 | input | DIF1 selects the PCM data length (L: 24-bit, H: 32-bit); DSDSEL1 controls the DSD sampling rate. |
| 39 | TDM0 | input | TDM interface format select; must be fixed to L in DSD mode. |
| 40 | TDM1 | input | TDM interface format select; must be fixed to L in DSD mode. |
| 41 | PSN/CAD0_SPI | input | PSN selects I2C bus (L) or parallel (H) control when the I2C pin is H; CAD0_SPI is the chip address 0 pin in 3-wire mode when the I2C pin is L. |
| 42 | I2C | input | Control mode select: L selects 3-wire serial control, H selects I2C bus or parallel control. |
| 43 | DP | input | DSD mode enable: L selects PCM mode, H selects DSD mode. |
| 44 | HPFE/DCKS | input | HPFE enables the digital high-pass filter in PCM mode (L: disable, H: enable); DCKS selects the master clock frequency in DSD mode. |
| 45 | LDOE | input | LDO enable: L disables and H enables the internal LDO; pin is pulled down by 100 kΩ internally. |
| 46 | ODP | input | Optimal data placement mode enable pin. |
| 47 | AIN1P | input | Channel 1 positive analog input pin. |
| 48 | AIN1N | input | Channel 1 negative analog input pin. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | QFN-48-EP(7x7) |
| Category | ADC/DAC/Data Conversion |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog supply (AVDD pin) absolute maximum | AVDDam | -0.3 | 6 | V | VSS=0 V; Note 3 | 8 | |
| Digital interface supply (TVDD pin) absolute maximum | TVDDam | -0.3 | 4 | V | VSS=0 V; Note 3 | 8 | |
| Digital core supply (VDD18 pin) absolute maximum | VDD18am | -0.3 | 2.5 | V | VSS=0 V; Note 3, Note 4 (LDOE pin = L) | 8 | |
| Input current (any pin except supplies) | IIN | 10 | mA | 8 | |||
| Analog input voltage (AIN1-4P, AIN1-4N pins) | VINA | -0.3 | V | Printed max is AVDD+0.3 V; VSS=0 V | 8 | ||
| Digital input voltage | VIND | -0.3 | V | Printed max is TVDD+0.3 V; VSS=0 V | 8 | ||
| Ambient temperature, power applied (back tab connected to VSS) | Ta | -40 | 105 | °C | Power applied; back tab connected to VSS | 8 | |
| Ambient temperature, power applied (back tab open) | Ta | -40 | 70 | °C | Power applied; back tab open | 8 | |
| Storage temperature | Tstg | -65 | 150 | °C | 8 | ||
| Analog supply (AVDD pin) | AVDD | 4.5 | 5 | 5.5 | V | LDOE pin = L; Note 5 | 8 |
| Digital interface supply (TVDD pin), LDOE pin = L | TVDD | 1.7 | 1.8 | 1.98 | V | LDOE pin = L; Note 6: must not exceed VDD18±0.1 V | 8 |
| Digital core supply (VDD18 pin), LDOE pin = L | VDD18 | 1.7 | 1.8 | 1.98 | V | LDOE pin = L | 8 |
| Digital interface supply (TVDD pin), LDOE pin = H | TVDD | 3 | 3.3 | 3.6 | V | LDOE pin = H; Note 7 | 8 |
| Voltage reference high (VREFH1) | VREFH1 | 4.5 | 5 | 5.5 | V | Note 8: must not exceed AVDD+0.1 V | 8 |
| Input voltage (full scale, differential) | 2.7 | 2.8 | 2.9 | Vpp | Note 10: (AINnP)−(AINnN) at ADC full scale | 9 | |
| S/(N+D) fs=48kHz, −1dBFS | S/(N+D) | 100 | 106 | dB | Ta=25°C; AVDD=5.0 V; TVDD=3.3 V; fs=48 kHz; BW=20 kHz; −1 dBFS | 9 | |
| Dynamic range (Not Sum. mode) | 110 | 115 | dB | Ta=25°C; AVDD=5.0 V; −60 dBFS, A-weighted; Not Sum. mode | 9 | ||
| S/N (Not Sum. mode) | S/N | 110 | 115 | dB | Ta=25°C; AVDD=5.0 V; A-weighted; Not Sum. mode | 9 | |
| Input resistance | 8.8 | 10.4 | 12 | kΩ | Doubled in DSD 64fs mode (DSD128/256 values as shown) | 9 | |
| Interchannel isolation (AIN1-AIN2) | 110 | 120 | dB | AIN1-AIN2 | 9 | ||
| Interchannel gain mismatch | 0 | 0.5 | dB | 9 | |||
| Power supply current, AVDD+VREFH1 | 12 | 16 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power supply current, TVDD (fs=48 kHz) | 7 | 10 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power supply current, TVDD (fs=96 kHz) | 11 | 14 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power supply current, TVDD (fs=192 kHz) | 11 | 14 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power-down supply current, AVDD+TVDD | 10 | 100 | µA | PDN pin = L; Note 12: all digital inputs fixed to TVDD or TVSS | 9 | ||
| Passband, sharp roll-off (fs=48 kHz) | PB | 0 | 22 | kHz | +0.001/−0.06 dB; SD pin = L, SLOW pin = L | 10 | |
| Stopband, sharp roll-off (fs=48 kHz) | SB | 27.9 | kHz | SD pin = L, SLOW pin = L | 10 | ||
| Passband, slow roll-off (fs=48 kHz) | PB | 0 | 21.9 | kHz | +0.001/−0.076 dB; SD pin = L, SLOW pin = H | 10 | |
| Stopband, slow roll-off (fs=48 kHz) | SB | 36.5 | kHz | SD pin = L, SLOW pin = H | 10 | ||
| Passband, short delay sharp roll-off (fs=48 kHz) | PB | 0 | 22 | kHz | +0.001/−0.06 dB; SD pin = H, SLOW pin = L | 10 | |
| Stopband, short delay sharp roll-off (fs=48 kHz) | SB | 27.9 | kHz | SD pin = H, SLOW pin = L | 10 | ||
| Passband, short delay slow roll-off (fs=48 kHz) | PB | 0 | 21.9 | kHz | +0.001/−0.076 dB; SD pin = H, SLOW pin = H | 10 | |
| Stopband, short delay slow roll-off (fs=48 kHz) | SB | 36.5 | kHz | SD pin = H, SLOW pin = H | 10 | ||
| Stopband, sharp roll-off (fs=96 kHz) | SB | 55.7 | kHz | SD pin = L, SLOW pin = L | 12 | ||
| Stopband, slow roll-off (fs=96 kHz) | SB | 73 | kHz | SD pin = L, SLOW pin = H | 12 | ||
| Passband, short delay sharp roll-off (fs=96 kHz) | PB | 0 | 44.1 | kHz | +0.001/−0.06 dB; SD pin = H, SLOW pin = L | 12 | |
| Stopband, short delay sharp roll-off (fs=96 kHz) | SB | 55.7 | kHz | SD pin = H, SLOW pin = L | 12 | ||
| Passband, short delay slow roll-off (fs=96 kHz) | PB | 0 | 25 | kHz | +0.001/−0.076 dB; SD pin = H, SLOW pin = H | 12 | |
| Stopband, short delay slow roll-off (fs=96 kHz) | SB | 73 | kHz | SD pin = H, SLOW pin = H | 12 | ||
| Stopband, sharp roll-off (fs=192 kHz) | SB | 122.9 | kHz | SD pin = L, SLOW pin = L | 14 | ||
| Stopband, slow roll-off (fs=192 kHz) | SB | 146 | kHz | SD pin = L, SLOW pin = H | 14 | ||
| Passband, short delay sharp roll-off (fs=192 kHz) | PB | 0 | 83.7 | kHz | +0.001/−0.037 dB; SD pin = H, SLOW pin = L | 14 | |
| Stopband, short delay sharp roll-off (fs=192 kHz) | SB | 122.9 | kHz | SD pin = H, SLOW pin = L | 14 | ||
| Passband, short delay slow roll-off (fs=192 kHz) | PB | 0 | 31.5 | kHz | +0.001/−0.1 dB; SD pin = H, SLOW pin = H | 14 | |
| Stopband, short delay slow roll-off (fs=192 kHz) | SB | 146 | kHz | SD pin = H, SLOW pin = H | 14 | ||
| Stopband (fs=384 kHz) | SB | 277.4 | kHz | Digital decimation LPF; does not depend on SD or SLOW pin | 16 | ||
| Stopband (fs=768 kHz) | SB | 640.3 | kHz | Digital decimation LPF; does not depend on SD or SLOW pin | 17 | ||
| High-level input voltage, TVDD=3.0-3.6 V | VIH | 70 | %TVDD | TVDD=3.0-3.6 V (LDOE pin = H) | 18 | ||
| Low-level input voltage, TVDD=3.0-3.6 V | VIL | 30 | %TVDD | TVDD=3.0-3.6 V (LDOE pin = H) | 18 | ||
| High-level output voltage, TVDD=3.0-3.6 V | VOH | -0.5 | V | Printed min is TVDD−0.5 V; Iout=−100 µA; TVDD=3.0-3.6 V (LDOE pin = H) | 18 | ||
| Low-level output voltage (except SDA), TVDD=3.0-3.6 V | VOL | 0.5 | V | Iout=100 µA; TVDD=3.0-3.6 V (LDOE pin = H) | 18 | ||
| Low-level output voltage (SDA pin), TVDD=3.0-3.6 V | VOL | 0.4 | V | SDA pin: Iout=3 mA; TVDD=3.0-3.6 V (LDOE pin = H) | 18 | ||
| High-level input voltage, TVDD=1.7-1.98 V | VIH | 80 | %TVDD | TVDD=1.7-1.98 V (LDOE pin = L) | 18 | ||
| Low-level input voltage, TVDD=1.7-1.98 V | VIL | 20 | %TVDD | TVDD=1.7-1.98 V (LDOE pin = L) | 18 | ||
| High-level output voltage, TVDD=1.7-1.98 V | VOH | -0.3 | V | Printed min is TVDD−0.3 V; Iout=−100 µA; TVDD=1.7-1.98 V (LDOE pin = L) | 18 | ||
| Low-level output voltage (except SDA), TVDD=1.7-1.98 V | VOL | 0.3 | V | Iout=100 µA; TVDD=1.7-1.98 V (LDOE pin = L) | 18 | ||
| Low-level output voltage (SDA pin), TVDD=1.7-1.98 V | VOL | 20 | %TVDD | SDA pin: Iout=3 mA; TVDD=1.7-1.98 V (LDOE pin = L) | 18 | ||
| Input leakage current | Iin | 10 | µA | 18 |
CAD (KiCad official)
- Symbol:
AK5552VN - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ak5552vn-etched.step/ak5552vn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ak5552vn.step/ak5552vn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Asahi Kasei Microdevices datasheet (70 pp, sha256
fe291e7aec8567ce, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).