component
AK5538VN
Public Made by Adomby adom
Asahi Kasei Microdevices Analog To Digital Converters (ADCs), QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AK5538VN
Asahi Kasei Microdevices · Analog To Digital Converters (ADCs) · QFN-64-EP(9x9)
AK5538VN from Asahi Kasei Microdevices, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVSS1 | power_in | Analog ground pin for AIN1-4, which must be connected to the same analog ground plane as DVSS and AVSS2. |
| 2 | AVDD1 | power_in | Analog power supply pin for AIN1-4, specified at 3.0-3.6 V. |
| 3 | AIN3P | input | Channel 3 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 4 | AIN3N | input | Channel 3 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 5 | VREFL2 | input | ADC low-level voltage reference input for channels 3-4, normally connected to AVSS. |
| 6 | VREFH2 | input | ADC high-level voltage reference input for channels 3-4, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 7 | AIN4N | input | Channel 4 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 8 | AIN4P | input | Channel 4 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 9 | AIN5P | input | Channel 5 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 10 | AIN5N | input | Channel 5 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 11 | VREFH3 | input | ADC high-level voltage reference input for channels 5-6, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 12 | VREFL3 | input | ADC low-level voltage reference input for channels 5-6, normally connected to AVSS. |
| 13 | AIN6N | input | Channel 6 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 14 | AIN6P | input | Channel 6 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 15 | AVDD2 | power_in | Analog power supply pin for AIN5-8, specified at 3.0-3.6 V. |
| 16 | AVSS2 | power_in | Analog ground pin for AIN5-8, which must be connected to the same analog ground plane as DVSS and AVSS1. |
| 17 | AIN7P | input | Channel 7 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 18 | AIN7N | input | Channel 7 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 19 | VREFH4 | input | ADC high-level voltage reference input for channels 7-8, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 20 | VREFL4 | input | ADC low-level voltage reference input for channels 7-8, normally connected to AVSS. |
| 21 | AIN8N | input | Channel 8 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 22 | AIN8P | input | Channel 8 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 23 | TEST | input | Test enable pin with an internal 100 kΩ pull-down; it must be connected to DVSS in normal use. |
| 24 | MCLK | input | Master clock input pin for the device. |
| 25 | TVDD | power_in | Digital I/O buffer and LDO power supply, 1.7-1.98 V when LDOE is L or 3.0-3.6 V when LDOE is H; TVDD must not exceed VDD18±0.1 V when LDOE is L. |
| 26 | DVSS | power_in | Digital ground pin, which must be connected to the same analog ground plane as AVSS1/2. |
| 27 | VDD18 | power_in | Digital core power supply, 1.7-1.98 V when LDOE is L; when LDOE is H this pin is the LDO stabilization capacitor connection and cannot supply external circuits. |
| 28 | PDN | input | Reset and power-down pin: L resets the device and powers it down, H enables normal operation. |
| 29 | PW0 | input | Power management pin that also selects channel summation mode. |
| 30 | PW1 | input | Power management pin that also selects channel summation mode. |
| 31 | PW2 | input | Power management pin that also selects channel summation mode. |
| 32 | MSN | input | Master/slave select: L selects slave mode and H selects master mode. |
| 33 | BICK/DCLK | bidirectional | In PCM slave mode this is the audio serial data clock input, in PCM master mode it is the serial data clock output, and in DSD mode it is the DSD clock output; it has an internal 100 kΩ pull-down. |
| 34 | LRCK/DSDOL1 | bidirectional | In PCM slave mode this is the channel clock input, in PCM master mode it is the channel clock output, and in DSD mode it outputs the AIN1 DSD serial data; it has an internal 100 kΩ pull-down. |
| 35 | TDMIN/DSDOR1 | bidirectional | In PCM mode this is the TDM data input with an internal 100 kΩ pull-down, and in DSD mode it outputs the AIN2 DSD serial data. |
| 36 | SDTO1/DSDOL2 | output | In PCM mode this outputs serial data for AIN1 and AIN2, and in DSD mode it outputs AIN3 DSD data; it is Low when powered down. |
| 37 | SDTO2/DSDOR2 | output | In PCM mode this outputs serial data for AIN3 and AIN4, and in DSD mode it outputs AIN4 DSD data; it is Low when powered down. |
| 38 | SDTO3/DSDOL3 | output | In PCM mode this outputs serial data for AIN5 and AIN6, and in DSD mode it outputs AIN5 DSD data; it is Low when powered down. |
| 39 | SDTO4/DSDOR3 | output | In PCM mode this outputs serial data for AIN7 and AIN8, and in DSD mode it outputs AIN6 DSD data; it is Low when powered down. |
| 40 | DSDOL4 | output | DSD serial data output for AIN7; it is Low when powered down. |
| 41 | DSDOR4 | output | DSD serial data output for AIN8; it is Low when powered down. |
| 42 | OVF | output | Analog input overflow flag output that goes High when any of AIN1-8 exceeds 0.3 dBFS in PCM mode, or when a DSD modulator overflows in DSD mode. |
| 43 | CKS0/SDA/CDTI | bidirectional | Clock mode select input in general use, serving as the I2C control data I/O (SDA) in I2C mode or the control data input (CDTI) in 3-wire mode. |
| 44 | CKS1/CAD0_I2C/CSN | input | Clock mode select input in general use, serving as chip address 0 in I2C mode or chip select (CSN) in 3-wire mode. |
| 45 | CKS2/SCL/CCLK | input | Clock mode select input in general use, serving as the I2C control clock (SCL) in I2C mode or the 3-wire control clock (CCLK) in 3-wire mode. |
| 46 | CKS3/CAD1 | input | Clock mode select input in general use, serving as chip address 1 in I2C or 3-wire control mode. |
| 47 | SLOW/DCKB | input | Selects the slow roll-off digital filter in PCM mode, or sets the DCLK polarity in DSD mode. |
| 48 | SD/PMOD | input | Selects the short-delay digital filter in PCM mode, or enables DSD phase modulation mode in DSD mode. |
| 49 | DIF0/DSDSEL0 | input | In PCM mode selects the audio data format (L: MSB justified, H: I2S); in DSD mode sets the DSD sampling rate control. |
| 50 | DIF1/DSDSEL1 | input | In PCM mode selects the word length (L: 24-bit, H: 32-bit); in DSD mode sets the DSD sampling rate control. |
| 51 | TDM0 | input | TDM interface format select pin, which must be fixed to L when using DSD mode. |
| 52 | TDM1 | input | TDM interface format select pin, which must be fixed to L when using DSD mode. |
| 53 | PSN/CAD0_SPI | input | With I2C pin High it selects control mode (L: I2C bus serial control, H: parallel control); with I2C pin Low it serves as chip address 0 for 3-wire control. |
| 54 | I2C | input | Control mode select: L selects 3-wire serial control and H selects I2C bus or parallel control. |
| 55 | DP | input | DSD mode enable: L selects PCM mode and H selects DSD mode. |
| 56 | DCKS/HPFE | input | High-pass filter enable (L: disable, H: enable) in PCM mode, and master clock frequency select (DCKS) in DSD mode. |
| 57 | LDOE | input | LDO enable: L disables and H enables the internal LDO; the pin has an internal 100 kΩ pull-down and all digital inputs must not float. |
| 58 | ODP | input | Optimal data placement mode select pin. |
| 59 | AIN1P | input | Channel 1 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 60 | AIN1N | input | Channel 1 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 61 | VREFL1 | input | ADC low-level voltage reference input for channels 1-2, normally connected to AVSS. |
| 62 | VREFH1 | input | ADC high-level voltage reference input for channels 1-2, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 63 | AIN2N | input | Channel 2 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 64 | AIN2P | input | Channel 2 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | QFN-64-EP(9x9) |
| Category | ADC/DAC/Data Conversion |
| Pins | 65 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Power Supply (AVDD pin) | AVDDam | -0.3 | 6 | V | 8 | ||
| Digital Interface Power Supply (TVDD pin) | TVDDam | -0.3 | 4 | V | 8 | ||
| Digital Core Power Supply (VDD18 pin) | VDD18am | -0.3 | 2.5 | V | Note 4: 1.8 V LDO off (LDOE pin = L), external power supplied to VDD18 | 8 | |
| Input Current (Any Pin Except Supplies) | IIN | 10 | mA | 8 | |||
| Analog Input Voltage (AIN1-4P, AIN1-4N pins) | VINA | -0.3 | V | max printed as AVDD+0.3 V | 8 | ||
| Digital Input Voltage | VIND | -0.3 | V | max printed as TVDD+0.3 V | 8 | ||
| Ambient Temperature (Power applied) | Ta | -40 | 105 | °C | When the back tab is connected to VSS | 8 | |
| Ambient Temperature (Power applied) | Ta | -40 | 70 | °C | When the back tab is open | 8 | |
| Storage Temperature | Tstg | -65 | 150 | °C | 8 | ||
| Analog Power Supply (AVDD pin) | AVDD | 3 | 3.3 | 3.6 | V | LDOE pin = L (Note 5) | 8 |
| Digital Interface Power Supply (TVDD pin) | TVDD | 1.7 | 1.8 | 1.98 | V | Note 6: TVDD must not exceed VDD18±0.1 V when LDOE pin = L | 8 |
| Digital Core Power Supply (VDD18 pin) | VDD18 | 1.7 | 1.8 | 1.98 | V | LDOE pin = L | 8 |
| Digital Interface Power Supply (TVDD pin) | TVDD | 3 | 3.3 | 3.6 | V | LDOE pin = H (Note 7) | 8 |
| Voltage Reference High (VREFH1-4) | VREFH1-4 | 3 | 3.3 | 3.6 | V | Note 8: VREFH1-4 must not exceed AVDD+0.1 V | 8 |
| Analog Input Voltage (full scale, AINnP-AINnN) | 1.75 | 1.85 | 1.95 | Vpp | Ta=25 C; AVDD=3.3 V; TVDD=3.3 V; fs=48 kHz (Note 10) | 9 | |
| S/(N+D) at 1 dBFS | 97 | 103 | dB | fs=48 kHz; BW=20 kHz; 1 dBFS | 9 | ||
| Dynamic Range (60 dBFS, A-weighted), Not-Sum mode | 106 | 111 | dB | 60 dBFS with A-weighted; Not-Sum mode | 9 | ||
| S/N (A-weighted), Not-Sum mode | 106 | 111 | dB | A-weighted; Not-Sum mode | 9 | ||
| Input Resistance | 8.8 | 10.4 | 12 | k | Values doubled in DSD 64fs mode; DSD128/256 values as shown | 9 | |
| Interchannel Isolation | 110 | 120 | dB | AIN1↔AIN2, AIN3↔AIN4, AIN5↔AIN6, AIN7↔AIN8 | 9 | ||
| Interchannel Gain Mismatch | 0 | 0.5 | dB | 9 | |||
| Power Supply Current, AVDD + VREFHm (m=1-4) | 38 | 50 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, TVDD (fs=48 kHz) | 17 | 22 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, TVDD (fs=96 kHz) | 28 | 36 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, TVDD (fs=192 kHz) | 25 | 32 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 | ||
| Power Down Mode Current, AVDD+TVDD | 10 | 100 | µA | PDN pin = L; all digital inputs fixed to TVDD or TVSS (Note 12) | 9 | ||
| Input Leakage Current | Iin | 10 | µA | 18 | |||
| Low-Level Output Voltage (except SDA pin) | VOL | 0.5 | V | TVDD=3.0-3.6 V (LDOE pin=H); Iout=100 µA | 18 | ||
| Low-Level Output Voltage (SDA pin) | VOL | 0.4 | V | TVDD=3.0-3.6 V (LDOE pin=H); SDA pin Iout=3 mA | 18 | ||
| Low-Level Output Voltage (except SDA pin) | VOL | 0.3 | V | TVDD=1.7-1.98 V (LDOE pin=L); Iout=100 µA | 18 | ||
| Master Clock Frequency | fCLK | 2.048 | 49.152 | MHz | 19 | ||
| Master Clock Duty Cycle | dCLK | 45 | 55 | % | 19 | ||
| Passband (+0.001/0.06 dB), fs=48 kHz sharp roll-off | PB | 0 | 22 | kHz | SD pin = L; SLOW pin = L | 10 | |
| Stopband, fs=48 kHz sharp roll-off | SB | 27.9 | kHz | SD pin = L; SLOW pin = L | 10 | ||
| Stopband Attenuation, fs=48 kHz sharp roll-off | SA | 85 | dB | SD pin = L; SLOW pin = L | 10 | ||
| Passband (+0.001/0.076 dB), fs=48 kHz slow roll-off | PB | 0 | 21.9 | kHz | SD pin = L; SLOW pin = H | 10 | |
| Stopband, fs=48 kHz slow roll-off | SB | 36.5 | kHz | SD pin = L; SLOW pin = H | 10 | ||
| Stopband Attenuation, fs=48 kHz slow roll-off | SA | 85 | dB | SD pin = L; SLOW pin = H | 10 | ||
| Stopband, fs=96 kHz sharp roll-off | SB | 55.7 | kHz | SD pin = L; SLOW pin = L | 12 | ||
| Stopband Attenuation, fs=96 kHz sharp roll-off | SA | 85 | dB | SD pin = L; SLOW pin = L | 12 | ||
| Stopband, fs=96 kHz slow roll-off | SB | 73 | kHz | SD pin = L; SLOW pin = H | 12 | ||
| Stopband Attenuation, fs=96 kHz slow roll-off | SA | 85 | dB | SD pin = L; SLOW pin = H | 12 | ||
| Stopband, fs=192 kHz sharp roll-off | SB | 122.9 | kHz | SD pin = L; SLOW pin = L | 14 | ||
| Stopband Attenuation, fs=192 kHz sharp roll-off | SA | 85 | dB | SD pin = L; SLOW pin = L | 14 | ||
| Stopband, fs=192 kHz slow roll-off | SB | 146 | kHz | SD pin = L; SLOW pin = H | 14 | ||
| Stopband Attenuation, fs=192 kHz slow roll-off | SA | 85 | dB | SD pin = L; SLOW pin = H | 14 | ||
| Stopband, fs=384 kHz | SB | 277.4 | kHz | Does not depend on SD or SLOW pins | 16 | ||
| Stopband Attenuation, fs=384 kHz | SA | 85 | dB | Does not depend on SD or SLOW pins | 16 | ||
| Stopband, fs=768 kHz | SB | 640.3 | kHz | Does not depend on SD or SLOW pins | 17 | ||
| Stopband Attenuation, fs=768 kHz | SA | 85 | dB | Does not depend on SD or SLOW pins | 17 |
CAD (KiCad official)
- Symbol:
AK5538VN - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
ak5538vn-etched.step/ak5538vn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ak5538vn.step/ak5538vn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Asahi Kasei Microdevices datasheet (70 pp, sha256
731b6e9f0f30cc31, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AK5538VN
**Asahi Kasei Microdevices** · Analog To Digital Converters (ADCs) · QFN-64-EP(9x9)
AK5538VN from Asahi Kasei Microdevices, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVSS1 | power_in | Analog ground pin for AIN1-4, which must be connected to the same analog ground plane as DVSS and AVSS2. |
| 2 | AVDD1 | power_in | Analog power supply pin for AIN1-4, specified at 3.0-3.6 V. |
| 3 | AIN3P | input | Channel 3 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 4 | AIN3N | input | Channel 3 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 5 | VREFL2 | input | ADC low-level voltage reference input for channels 3-4, normally connected to AVSS. |
| 6 | VREFH2 | input | ADC high-level voltage reference input for channels 3-4, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 7 | AIN4N | input | Channel 4 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 8 | AIN4P | input | Channel 4 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 9 | AIN5P | input | Channel 5 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 10 | AIN5N | input | Channel 5 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 11 | VREFH3 | input | ADC high-level voltage reference input for channels 5-6, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 12 | VREFL3 | input | ADC low-level voltage reference input for channels 5-6, normally connected to AVSS. |
| 13 | AIN6N | input | Channel 6 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 14 | AIN6P | input | Channel 6 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 15 | AVDD2 | power_in | Analog power supply pin for AIN5-8, specified at 3.0-3.6 V. |
| 16 | AVSS2 | power_in | Analog ground pin for AIN5-8, which must be connected to the same analog ground plane as DVSS and AVSS1. |
| 17 | AIN7P | input | Channel 7 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 18 | AIN7N | input | Channel 7 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 19 | VREFH4 | input | ADC high-level voltage reference input for channels 7-8, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 20 | VREFL4 | input | ADC low-level voltage reference input for channels 7-8, normally connected to AVSS. |
| 21 | AIN8N | input | Channel 8 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 22 | AIN8P | input | Channel 8 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 23 | TEST | input | Test enable pin with an internal 100 kΩ pull-down; it must be connected to DVSS in normal use. |
| 24 | MCLK | input | Master clock input pin for the device. |
| 25 | TVDD | power_in | Digital I/O buffer and LDO power supply, 1.7-1.98 V when LDOE is L or 3.0-3.6 V when LDOE is H; TVDD must not exceed VDD18±0.1 V when LDOE is L. |
| 26 | DVSS | power_in | Digital ground pin, which must be connected to the same analog ground plane as AVSS1/2. |
| 27 | VDD18 | power_in | Digital core power supply, 1.7-1.98 V when LDOE is L; when LDOE is H this pin is the LDO stabilization capacitor connection and cannot supply external circuits. |
| 28 | PDN | input | Reset and power-down pin: L resets the device and powers it down, H enables normal operation. |
| 29 | PW0 | input | Power management pin that also selects channel summation mode. |
| 30 | PW1 | input | Power management pin that also selects channel summation mode. |
| 31 | PW2 | input | Power management pin that also selects channel summation mode. |
| 32 | MSN | input | Master/slave select: L selects slave mode and H selects master mode. |
| 33 | BICK/DCLK | bidirectional | In PCM slave mode this is the audio serial data clock input, in PCM master mode it is the serial data clock output, and in DSD mode it is the DSD clock output; it has an internal 100 kΩ pull-down. |
| 34 | LRCK/DSDOL1 | bidirectional | In PCM slave mode this is the channel clock input, in PCM master mode it is the channel clock output, and in DSD mode it outputs the AIN1 DSD serial data; it has an internal 100 kΩ pull-down. |
| 35 | TDMIN/DSDOR1 | bidirectional | In PCM mode this is the TDM data input with an internal 100 kΩ pull-down, and in DSD mode it outputs the AIN2 DSD serial data. |
| 36 | SDTO1/DSDOL2 | output | In PCM mode this outputs serial data for AIN1 and AIN2, and in DSD mode it outputs AIN3 DSD data; it is Low when powered down. |
| 37 | SDTO2/DSDOR2 | output | In PCM mode this outputs serial data for AIN3 and AIN4, and in DSD mode it outputs AIN4 DSD data; it is Low when powered down. |
| 38 | SDTO3/DSDOL3 | output | In PCM mode this outputs serial data for AIN5 and AIN6, and in DSD mode it outputs AIN5 DSD data; it is Low when powered down. |
| 39 | SDTO4/DSDOR3 | output | In PCM mode this outputs serial data for AIN7 and AIN8, and in DSD mode it outputs AIN6 DSD data; it is Low when powered down. |
| 40 | DSDOL4 | output | DSD serial data output for AIN7; it is Low when powered down. |
| 41 | DSDOR4 | output | DSD serial data output for AIN8; it is Low when powered down. |
| 42 | OVF | output | Analog input overflow flag output that goes High when any of AIN1-8 exceeds 0.3 dBFS in PCM mode, or when a DSD modulator overflows in DSD mode. |
| 43 | CKS0/SDA/CDTI | bidirectional | Clock mode select input in general use, serving as the I2C control data I/O (SDA) in I2C mode or the control data input (CDTI) in 3-wire mode. |
| 44 | CKS1/CAD0_I2C/CSN | input | Clock mode select input in general use, serving as chip address 0 in I2C mode or chip select (CSN) in 3-wire mode. |
| 45 | CKS2/SCL/CCLK | input | Clock mode select input in general use, serving as the I2C control clock (SCL) in I2C mode or the 3-wire control clock (CCLK) in 3-wire mode. |
| 46 | CKS3/CAD1 | input | Clock mode select input in general use, serving as chip address 1 in I2C or 3-wire control mode. |
| 47 | SLOW/DCKB | input | Selects the slow roll-off digital filter in PCM mode, or sets the DCLK polarity in DSD mode. |
| 48 | SD/PMOD | input | Selects the short-delay digital filter in PCM mode, or enables DSD phase modulation mode in DSD mode. |
| 49 | DIF0/DSDSEL0 | input | In PCM mode selects the audio data format (L: MSB justified, H: I2S); in DSD mode sets the DSD sampling rate control. |
| 50 | DIF1/DSDSEL1 | input | In PCM mode selects the word length (L: 24-bit, H: 32-bit); in DSD mode sets the DSD sampling rate control. |
| 51 | TDM0 | input | TDM interface format select pin, which must be fixed to L when using DSD mode. |
| 52 | TDM1 | input | TDM interface format select pin, which must be fixed to L when using DSD mode. |
| 53 | PSN/CAD0_SPI | input | With I2C pin High it selects control mode (L: I2C bus serial control, H: parallel control); with I2C pin Low it serves as chip address 0 for 3-wire control. |
| 54 | I2C | input | Control mode select: L selects 3-wire serial control and H selects I2C bus or parallel control. |
| 55 | DP | input | DSD mode enable: L selects PCM mode and H selects DSD mode. |
| 56 | DCKS/HPFE | input | High-pass filter enable (L: disable, H: enable) in PCM mode, and master clock frequency select (DCKS) in DSD mode. |
| 57 | LDOE | input | LDO enable: L disables and H enables the internal LDO; the pin has an internal 100 kΩ pull-down and all digital inputs must not float. |
| 58 | ODP | input | Optimal data placement mode select pin. |
| 59 | AIN1P | input | Channel 1 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 60 | AIN1N | input | Channel 1 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 61 | VREFL1 | input | ADC low-level voltage reference input for channels 1-2, normally connected to AVSS. |
| 62 | VREFH1 | input | ADC high-level voltage reference input for channels 1-2, specified at 3.0-3.3-3.6 V and not to exceed AVDD+0.1 V. |
| 63 | AIN2N | input | Channel 2 negative differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 64 | AIN2P | input | Channel 2 positive differential analog input; full-scale is nominally ±1.85 V (typ) and inputs must not exceed AVDD+0.3 V or AVSS-0.3 V. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | QFN-64-EP(9x9) |
| Category | ADC/DAC/Data Conversion |
| Pins | 65 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog Power Supply (AVDD pin) | AVDDam | -0.3 | | 6 | V | | 8 |
| Digital Interface Power Supply (TVDD pin) | TVDDam | -0.3 | | 4 | V | | 8 |
| Digital Core Power Supply (VDD18 pin) | VDD18am | -0.3 | | 2.5 | V | Note 4: 1.8 V LDO off (LDOE pin = L), external power supplied to VDD18 | 8 |
| Input Current (Any Pin Except Supplies) | IIN | | | 10 | mA | | 8 |
| Analog Input Voltage (AIN1-4P, AIN1-4N pins) | VINA | -0.3 | | | V | max printed as AVDD+0.3 V | 8 |
| Digital Input Voltage | VIND | -0.3 | | | V | max printed as TVDD+0.3 V | 8 |
| Ambient Temperature (Power applied) | Ta | -40 | | 105 | °C | When the back tab is connected to VSS | 8 |
| Ambient Temperature (Power applied) | Ta | -40 | | 70 | °C | When the back tab is open | 8 |
| Storage Temperature | Tstg | -65 | | 150 | °C | | 8 |
| Analog Power Supply (AVDD pin) | AVDD | 3 | 3.3 | 3.6 | V | LDOE pin = L (Note 5) | 8 |
| Digital Interface Power Supply (TVDD pin) | TVDD | 1.7 | 1.8 | 1.98 | V | Note 6: TVDD must not exceed VDD18±0.1 V when LDOE pin = L | 8 |
| Digital Core Power Supply (VDD18 pin) | VDD18 | 1.7 | 1.8 | 1.98 | V | LDOE pin = L | 8 |
| Digital Interface Power Supply (TVDD pin) | TVDD | 3 | 3.3 | 3.6 | V | LDOE pin = H (Note 7) | 8 |
| Voltage Reference High (VREFH1-4) | VREFH1-4 | 3 | 3.3 | 3.6 | V | Note 8: VREFH1-4 must not exceed AVDD+0.1 V | 8 |
| Analog Input Voltage (full scale, AINnP-AINnN) | | 1.75 | 1.85 | 1.95 | Vpp | Ta=25 C; AVDD=3.3 V; TVDD=3.3 V; fs=48 kHz (Note 10) | 9 |
| S/(N+D) at 1 dBFS | | 97 | 103 | | dB | fs=48 kHz; BW=20 kHz; 1 dBFS | 9 |
| Dynamic Range (60 dBFS, A-weighted), Not-Sum mode | | 106 | 111 | | dB | 60 dBFS with A-weighted; Not-Sum mode | 9 |
| S/N (A-weighted), Not-Sum mode | | 106 | 111 | | dB | A-weighted; Not-Sum mode | 9 |
| Input Resistance | | 8.8 | 10.4 | 12 | k | Values doubled in DSD 64fs mode; DSD128/256 values as shown | 9 |
| Interchannel Isolation | | 110 | 120 | | dB | AIN1↔AIN2, AIN3↔AIN4, AIN5↔AIN6, AIN7↔AIN8 | 9 |
| Interchannel Gain Mismatch | | | 0 | 0.5 | dB | | 9 |
| Power Supply Current, AVDD + VREFHm (m=1-4) | | | 38 | 50 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 |
| Power Supply Current, TVDD (fs=48 kHz) | | | 17 | 22 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 |
| Power Supply Current, TVDD (fs=96 kHz) | | | 28 | 36 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 |
| Power Supply Current, TVDD (fs=192 kHz) | | | 25 | 32 | mA | Normal operation: PDN pin = H, LDOE pin = H | 9 |
| Power Down Mode Current, AVDD+TVDD | | | 10 | 100 | µA | PDN pin = L; all digital inputs fixed to TVDD or TVSS (Note 12) | 9 |
| Input Leakage Current | Iin | | | 10 | µA | | 18 |
| Low-Level Output Voltage (except SDA pin) | VOL | | | 0.5 | V | TVDD=3.0-3.6 V (LDOE pin=H); Iout=100 µA | 18 |
| Low-Level Output Voltage (SDA pin) | VOL | | | 0.4 | V | TVDD=3.0-3.6 V (LDOE pin=H); SDA pin Iout=3 mA | 18 |
| Low-Level Output Voltage (except SDA pin) | VOL | | | 0.3 | V | TVDD=1.7-1.98 V (LDOE pin=L); Iout=100 µA | 18 |
| Master Clock Frequency | fCLK | 2.048 | | 49.152 | MHz | | 19 |
| Master Clock Duty Cycle | dCLK | 45 | | 55 | % | | 19 |
| Passband (+0.001/0.06 dB), fs=48 kHz sharp roll-off | PB | 0 | | 22 | kHz | SD pin = L; SLOW pin = L | 10 |
| Stopband, fs=48 kHz sharp roll-off | SB | 27.9 | | | kHz | SD pin = L; SLOW pin = L | 10 |
| Stopband Attenuation, fs=48 kHz sharp roll-off | SA | 85 | | | dB | SD pin = L; SLOW pin = L | 10 |
| Passband (+0.001/0.076 dB), fs=48 kHz slow roll-off | PB | 0 | | 21.9 | kHz | SD pin = L; SLOW pin = H | 10 |
| Stopband, fs=48 kHz slow roll-off | SB | 36.5 | | | kHz | SD pin = L; SLOW pin = H | 10 |
| Stopband Attenuation, fs=48 kHz slow roll-off | SA | 85 | | | dB | SD pin = L; SLOW pin = H | 10 |
| Stopband, fs=96 kHz sharp roll-off | SB | 55.7 | | | kHz | SD pin = L; SLOW pin = L | 12 |
| Stopband Attenuation, fs=96 kHz sharp roll-off | SA | 85 | | | dB | SD pin = L; SLOW pin = L | 12 |
| Stopband, fs=96 kHz slow roll-off | SB | 73 | | | kHz | SD pin = L; SLOW pin = H | 12 |
| Stopband Attenuation, fs=96 kHz slow roll-off | SA | 85 | | | dB | SD pin = L; SLOW pin = H | 12 |
| Stopband, fs=192 kHz sharp roll-off | SB | 122.9 | | | kHz | SD pin = L; SLOW pin = L | 14 |
| Stopband Attenuation, fs=192 kHz sharp roll-off | SA | 85 | | | dB | SD pin = L; SLOW pin = L | 14 |
| Stopband, fs=192 kHz slow roll-off | SB | 146 | | | kHz | SD pin = L; SLOW pin = H | 14 |
| Stopband Attenuation, fs=192 kHz slow roll-off | SA | 85 | | | dB | SD pin = L; SLOW pin = H | 14 |
| Stopband, fs=384 kHz | SB | 277.4 | | | kHz | Does not depend on SD or SLOW pins | 16 |
| Stopband Attenuation, fs=384 kHz | SA | 85 | | | dB | Does not depend on SD or SLOW pins | 16 |
| Stopband, fs=768 kHz | SB | 640.3 | | | kHz | Does not depend on SD or SLOW pins | 17 |
| Stopband Attenuation, fs=768 kHz | SA | 85 | | | dB | Does not depend on SD or SLOW pins | 17 |
## CAD (KiCad official)
- Symbol: `AK5538VN`
- Footprint: `Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm`
- 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files: `ak5538vn-etched.step` / `ak5538vn-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ak5538vn.step` / `ak5538vn.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Asahi Kasei Microdevices datasheet](docs/ak5538vn-datasheet.pdf) (70 pp, sha256 `731b6e9f0f30cc31`, retrieved 2026-10-30, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ak5538vn-datasheet.pdf)