AK4458VN

Asahi Kasei Microdevices · Global Sourcing Parts · QFN-48(7x7)

AK4458VN from Asahi Kasei Microdevices, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MCLK	input	External master clock input; in PCM mode the clock is divided automatically by fs auto-detection, and in DSD mode the rate is set by the DCKS bit.
2	BICK/DCLK	input	Audio serial data clock (BICK) in PCM mode and DSD clock (DCLK) in DSD mode; the pin is Hi-Z in power-down.
3	LRCK/DSDL1	input	Input channel clock (LRCK) in PCM mode and DSD Lch data input 1 (DSDL1) in DSD mode.
4	SDTI1/DSDR1	input	Audio serial data input 1 in PCM mode and DSD Rch data input 1 in DSD mode; must be connected to DVSS if unused.
5	SDTI2/DSDL2	input	Audio serial data input 2 in PCM mode and DSD Lch data input 2 in DSD mode; must be connected to DVSS if unused.
6	SDTI3/DSDR2/TDMO1	input	Audio serial data input 3 in PCM mode (100kΩ internal pull-down), DSD Rch data input 2 in DSD mode, and TDM serial data output 1 in daisy-chain mode; SDTI3 must be connected to DVSS if unused.
7	SDTI4/DSDL3/TDMO2	input	Audio serial data input 4 in PCM mode (100kΩ internal pull-down), DSD Lch data input 3 in DSD mode, and TDM serial data output 2 in daisy-chain mode; SDTI4 must be connected to DVSS if unused.
8	DSDR3	input	DSD Rch audio serial data input 3; must be connected to DVSS if unused.
9	DSDL4	input	DSD Lch audio serial data input 4; must be connected to DVSS if unused.
10	DSDR4	input	DSD Rch audio serial data input 4; must be connected to DVSS if unused.
11	DZF/SMUTE	output	Zero-input detect output (DZF) in I2C or 3-wire control mode, and soft-mute control input (SMUTE, 100kΩ pull-down) in parallel mode, where high starts soft mute; DZF must be left open if unused.
12	CAD1/DCHAIN	input	Chip address 0 pin (CAD1) in I2C or 3-wire mode, and daisy-chain mode select (DCHAIN) in parallel mode.
13	SDA/CDTI/TDM0	bidirectional	Control data I/O (SDA) in I2C mode, control data input (CDTI) in 3-wire mode, and TDM mode select (TDM0) in parallel mode.
14	SCL/CCLK/TDM1	input	Control data clock (SCL) in I2C mode, control data clock (CCLK) in 3-wire mode, and TDM mode select (TDM1) in parallel mode.
15	CAD0_I2C/CSN/DIF	input	Chip address 0 in I2C mode, chip select (CSN) in 3-wire mode, and audio data format select in parallel mode (L: 32-bit MSB, H: 32-bit I2S).
16	PS/CAD0_SPI	input	Control mode select when the I2C pin is high (L: I2C bus, H: parallel control), and chip address 0 in 3-wire mode when the I2C pin is low.
17	I2C	input	Control mode select: L selects 3-wire serial control, H selects I2C bus or parallel control.
18	AOUTL1P	output	Lch positive analog output 1; must be left open if unused.
19	AOUTL1N	output	Lch negative analog output 1; must be left open if unused.
20	VREFL1	input	Negative voltage reference input for DAC1, connected to AVSS.
21	VREFH1	input	Positive voltage reference input for DAC1, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD).
22	AOUTR1N	output	Rch negative analog output 1; must be left open if unused.
23	AOUTR1P	output	Rch positive analog output 1; must be left open if unused.
24	AOUTL2P	output	Lch positive analog output 2; must be left open if unused.
25	AOUTL2N	output	Lch negative analog output 2; must be left open if unused.
26	VREFL2	input	Negative voltage reference input for DAC2, connected to AVSS.
27	VREFH2	input	Positive voltage reference input for DAC2, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD).
28	AOUTR2N	output	Rch negative analog output 2; must be left open if unused.
29	AOUTR2P	output	Rch positive analog output 2; must be left open if unused.
30	AVSS	power_in	Analog ground; AVSS and DVSS must be connected to the same potential.
31	AVDD	power_in	Analog power supply, 3.0V to 5.5V.
32	AOUTL3P	output	Lch positive analog output 3; must be left open if unused.
33	AOUTL3N	output	Lch negative analog output 3; must be left open if unused.
34	VREFH3	input	Positive voltage reference input for DAC3, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD).
35	VREFL3	input	Negative voltage reference input for DAC3, connected to AVSS.
36	AOUTR3N	output	Rch negative analog output 3; must be left open if unused.
37	AOUTR3P	output	Rch positive analog output 3; must be left open if unused.
38	AOUTL4P	output	Lch positive analog output 4; must be left open if unused.
39	AOUTL4N	output	Lch negative analog output 4; must be left open if unused.
40	VREFH4	input	Positive voltage reference input for DAC4, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD).
41	VREFL4	input	Negative voltage reference input for DAC4, connected to AVSS.
42	AOUTR4N	output	Rch negative analog output 4; must be left open if unused.
43	AOUTR4P	output	Rch positive analog output 4; must be left open if unused.
44	LDOE	input	Internal LDO enable: L disables the internal LDO, H enables it.
45	TVDD	power_in	Digital I/O power supply, 3.0V to 3.6V per the pin table (recommended range 1.7V to 3.6V in the operating conditions).
46	DVSS	power_in	Digital ground; AVSS and DVSS must be connected to the same potential.
47	VDD18	power_out	LDO output of 1.8V nominal when LDOE is high, requiring a 1.0µF capacitor to DVSS; when LDOE is low it is a 1.8V power input instead.
48	PDN	input	Power-down and reset pin: when low the AK4458 is powered down and control registers reset to default.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Asahi Kasei Microdevices
Package	QFN-48(7x7)
Category	Global Sourcing Parts
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply difference /AVSS-DVSS/	/AVSS-DVSS/			0.3	V	AVSS=DVSS=0V; Note 5	10
Analog power supply	AVDD	-0.3		6	V	Referenced to ground (Note 5)	10
Digital I/O power supply	TVDD	-0.3		4	V	Referenced to ground (Note 5)	10
Digital core power supply	VDD18	-0.3		2.5	V	Referenced to ground (Note 5)	10
Input current, any pin except supplies	IIN			10	mA		10
Digital input voltage	VIND	-0.3			V	Max printed as TVDD+0.3 V	10
Ambient temperature (power applied)	Ta	-40		105	°C	Back pad connected to ground	10
Ambient temperature (power applied)	Ta	-40		85	°C	Back pad open	10
Storage temperature	Tstg	-65		150	°C		10
Analog power supply (LDOE pin = L)	AVDD	3	5	5.5	V	LDOE pin = L (Note 7)	10
THD+N (0dBFS)	THD+N		-107	-100	dB	AVDD=5.0V; fs=44.1kHz; BW=20kHz; 0dBFS	11
Dynamic range		110	115		dB	AVDD=5.0V; 60dBFS with A-weighted	11
S/N (A-weighted)		110	115		dB	AVDD=5.0V; A-weighted	11
Interchannel isolation		100	110		dB	AVDD=5.0V; 1kHz	11
Interchannel gain mismatch			0	0.3	dB	AVDD=5.0V	11
Output voltage		2.65	2.8	2.95	Vpp	AVDD=5.0V; 0dB, 1kHz sine (Note 13)	11
Load resistance		2			kΩ	AVDD=5.0V; AC load with DC cut capacitor (Note 14)	11
Load capacitance				30	pF	AVDD=5.0V (Note 14)	11
Power supply current, normal operation	AVDD		31	41	mA	AVDD=5.0V; PDN pin = H	11
Power supply current, normal operation (fs=44.1kHz)	TVDD		8	11	mA	AVDD=5.0V; PDN pin = H; fs=44.1kHz	11
Power supply current, normal operation (fs=96kHz)	TVDD		13	17	mA	AVDD=5.0V; PDN pin = H; fs=96kHz	11
Power supply current, normal operation (fs=192kHz)	TVDD		20	26	mA	AVDD=5.0V; PDN pin = H; fs=192kHz	11
Power-down current	AVDD+TVDD		1	100	µA	PDN pin = L (Note 15)	11
THD+N (0dBFS)	THD+N		-93	-86	dB	AVDD=3.3V; fs=44.1kHz; BW=20kHz; 0dBFS	12
Dynamic range		106	111		dB	AVDD=3.3V; 60dBFS with A-weighted	12
S/N (A-weighted)		106	111		dB	AVDD=3.3V; A-weighted	12
Interchannel isolation		100	110		dB	AVDD=3.3V; 1kHz	12
Interchannel gain mismatch			0	0.3	dB	AVDD=3.3V	12
Output voltage		1.66	1.85	2.04	Vpp	AVDD=3.3V; 0dB, 1kHz sine (Note 13)	12
Load resistance		2			kΩ	AVDD=3.3V; AC load with DC cut capacitor (Note 14)	12
Load capacitance				30	pF	AVDD=3.3V (Note 14)	12
High-level input voltage	VIH	80			%TVDD	TVDD=1.7 to 3.0V; Ta=-40 to 105°C	21
Low-level input voltage	VIL			20	%TVDD	TVDD=1.7 to 3.0V; Ta=-40 to 105°C	21
High-level input voltage	VIH	70			%TVDD	TVDD=3.0 to 3.6V; Ta=-40 to 105°C	21
Low-level input voltage	VIL			30	%TVDD	TVDD=3.0 to 3.6V; Ta=-40 to 105°C	21
Low-level output voltage	VOL			0.5	V	Except SDA pin; Iout=100µA	21
Low-level output voltage (SDA)	VOL			0.4	V	SDA pin, 2.0V≤TVDD≤3.6V; Iout=3mA	21
Low-level output voltage (SDA)	VOL			20	%TVDD	SDA pin, 1.7V≤TVDD≤2.0V; Iout=3mA	21
Input leakage current	Iin			10	µA		21
Master clock frequency	fCLK	2.048		49.152	MHz	Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF	22
Master clock duty cycle	dCLK	40		60	%	Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF	22
Master clock high pulse width	tCLKH	9.155			ns	Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF	22
Master clock low pulse width	tCLKL	9.155			ns	Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF	22
LRCK frequency, normal speed mode	fsn	8		54	kHz	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
LRCK frequency, double speed mode	fsd	54		108	kHz	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
LRCK frequency, quad speed mode	fsq	108		216	kHz	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
LRCK duty cycle	Duty	45		55	%	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
BICK pulse width low	tBCKL	9			nsec	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
BICK pulse width high	tBCKH	9			nsec	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
BICK to LRCK edge	tBLR	5			nsec	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
LRCK edge to BICK	tLRB	5			nsec	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
SDTI1/2/3/4 hold time	tSDH	5			nsec	Normal Mode (TDM1-0 bits = 00); CL=20pF	22
SDTI1/2/3/4 setup time	tSDS	5			nsec	Normal Mode (TDM1-0 bits = 00); CL=20pF	22

CAD (KiCad official)

Symbol: AK4458VN
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: QFN-48(7x7) (KiCad packages3D, STEP)
3D model files: ak4458vn-etched.step / ak4458vn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ak4458vn.step / ak4458vn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Asahi Kasei Microdevices datasheet (90 pp, sha256 1d837ff1e7301b22, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AK4458VN

**Asahi Kasei Microdevices** · Global Sourcing Parts · QFN-48(7x7)

AK4458VN from Asahi Kasei Microdevices, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLK | input | External master clock input; in PCM mode the clock is divided automatically by fs auto-detection, and in DSD mode the rate is set by the DCKS bit. |
| 2 | BICK/DCLK | input | Audio serial data clock (BICK) in PCM mode and DSD clock (DCLK) in DSD mode; the pin is Hi-Z in power-down. |
| 3 | LRCK/DSDL1 | input | Input channel clock (LRCK) in PCM mode and DSD Lch data input 1 (DSDL1) in DSD mode. |
| 4 | SDTI1/DSDR1 | input | Audio serial data input 1 in PCM mode and DSD Rch data input 1 in DSD mode; must be connected to DVSS if unused. |
| 5 | SDTI2/DSDL2 | input | Audio serial data input 2 in PCM mode and DSD Lch data input 2 in DSD mode; must be connected to DVSS if unused. |
| 6 | SDTI3/DSDR2/TDMO1 | input | Audio serial data input 3 in PCM mode (100kΩ internal pull-down), DSD Rch data input 2 in DSD mode, and TDM serial data output 1 in daisy-chain mode; SDTI3 must be connected to DVSS if unused. |
| 7 | SDTI4/DSDL3/TDMO2 | input | Audio serial data input 4 in PCM mode (100kΩ internal pull-down), DSD Lch data input 3 in DSD mode, and TDM serial data output 2 in daisy-chain mode; SDTI4 must be connected to DVSS if unused. |
| 8 | DSDR3 | input | DSD Rch audio serial data input 3; must be connected to DVSS if unused. |
| 9 | DSDL4 | input | DSD Lch audio serial data input 4; must be connected to DVSS if unused. |
| 10 | DSDR4 | input | DSD Rch audio serial data input 4; must be connected to DVSS if unused. |
| 11 | DZF/SMUTE | output | Zero-input detect output (DZF) in I2C or 3-wire control mode, and soft-mute control input (SMUTE, 100kΩ pull-down) in parallel mode, where high starts soft mute; DZF must be left open if unused. |
| 12 | CAD1/DCHAIN | input | Chip address 0 pin (CAD1) in I2C or 3-wire mode, and daisy-chain mode select (DCHAIN) in parallel mode. |
| 13 | SDA/CDTI/TDM0 | bidirectional | Control data I/O (SDA) in I2C mode, control data input (CDTI) in 3-wire mode, and TDM mode select (TDM0) in parallel mode. |
| 14 | SCL/CCLK/TDM1 | input | Control data clock (SCL) in I2C mode, control data clock (CCLK) in 3-wire mode, and TDM mode select (TDM1) in parallel mode. |
| 15 | CAD0_I2C/CSN/DIF | input | Chip address 0 in I2C mode, chip select (CSN) in 3-wire mode, and audio data format select in parallel mode (L: 32-bit MSB, H: 32-bit I2S). |
| 16 | PS/CAD0_SPI | input | Control mode select when the I2C pin is high (L: I2C bus, H: parallel control), and chip address 0 in 3-wire mode when the I2C pin is low. |
| 17 | I2C | input | Control mode select: L selects 3-wire serial control, H selects I2C bus or parallel control. |
| 18 | AOUTL1P | output | Lch positive analog output 1; must be left open if unused. |
| 19 | AOUTL1N | output | Lch negative analog output 1; must be left open if unused. |
| 20 | VREFL1 | input | Negative voltage reference input for DAC1, connected to AVSS. |
| 21 | VREFH1 | input | Positive voltage reference input for DAC1, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD). |
| 22 | AOUTR1N | output | Rch negative analog output 1; must be left open if unused. |
| 23 | AOUTR1P | output | Rch positive analog output 1; must be left open if unused. |
| 24 | AOUTL2P | output | Lch positive analog output 2; must be left open if unused. |
| 25 | AOUTL2N | output | Lch negative analog output 2; must be left open if unused. |
| 26 | VREFL2 | input | Negative voltage reference input for DAC2, connected to AVSS. |
| 27 | VREFH2 | input | Positive voltage reference input for DAC2, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD). |
| 28 | AOUTR2N | output | Rch negative analog output 2; must be left open if unused. |
| 29 | AOUTR2P | output | Rch positive analog output 2; must be left open if unused. |
| 30 | AVSS | power_in | Analog ground; AVSS and DVSS must be connected to the same potential. |
| 31 | AVDD | power_in | Analog power supply, 3.0V to 5.5V. |
| 32 | AOUTL3P | output | Lch positive analog output 3; must be left open if unused. |
| 33 | AOUTL3N | output | Lch negative analog output 3; must be left open if unused. |
| 34 | VREFH3 | input | Positive voltage reference input for DAC3, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD). |
| 35 | VREFL3 | input | Negative voltage reference input for DAC3, connected to AVSS. |
| 36 | AOUTR3N | output | Rch negative analog output 3; must be left open if unused. |
| 37 | AOUTR3P | output | Rch positive analog output 3; must be left open if unused. |
| 38 | AOUTL4P | output | Lch positive analog output 4; must be left open if unused. |
| 39 | AOUTL4N | output | Lch negative analog output 4; must be left open if unused. |
| 40 | VREFH4 | input | Positive voltage reference input for DAC4, connected to AVDD (VREFH1-4 must be AVDD−0.5V to AVDD). |
| 41 | VREFL4 | input | Negative voltage reference input for DAC4, connected to AVSS. |
| 42 | AOUTR4N | output | Rch negative analog output 4; must be left open if unused. |
| 43 | AOUTR4P | output | Rch positive analog output 4; must be left open if unused. |
| 44 | LDOE | input | Internal LDO enable: L disables the internal LDO, H enables it. |
| 45 | TVDD | power_in | Digital I/O power supply, 3.0V to 3.6V per the pin table (recommended range 1.7V to 3.6V in the operating conditions). |
| 46 | DVSS | power_in | Digital ground; AVSS and DVSS must be connected to the same potential. |
| 47 | VDD18 | power_out | LDO output of 1.8V nominal when LDOE is high, requiring a 1.0µF capacitor to DVSS; when LDOE is low it is a 1.8V power input instead. |
| 48 | PDN | input | Power-down and reset pin: when low the AK4458 is powered down and control registers reset to default. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | QFN-48(7x7) |
| Category | Global Sourcing Parts |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply difference /AVSS-DVSS/ | /AVSS-DVSS/ |  |  | 0.3 | V | AVSS=DVSS=0V; Note 5 | 10 |
| Analog power supply | AVDD | -0.3 |  | 6 | V | Referenced to ground (Note 5) | 10 |
| Digital I/O power supply | TVDD | -0.3 |  | 4 | V | Referenced to ground (Note 5) | 10 |
| Digital core power supply | VDD18 | -0.3 |  | 2.5 | V | Referenced to ground (Note 5) | 10 |
| Input current, any pin except supplies | IIN |  |  | 10 | mA |  | 10 |
| Digital input voltage | VIND | -0.3 |  |  | V | Max printed as TVDD+0.3 V | 10 |
| Ambient temperature (power applied) | Ta | -40 |  | 105 | °C | Back pad connected to ground | 10 |
| Ambient temperature (power applied) | Ta | -40 |  | 85 | °C | Back pad open | 10 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 10 |
| Analog power supply (LDOE pin = L) | AVDD | 3 | 5 | 5.5 | V | LDOE pin = L (Note 7) | 10 |
| THD+N (0dBFS) | THD+N |  | -107 | -100 | dB | AVDD=5.0V; fs=44.1kHz; BW=20kHz; 0dBFS | 11 |
| Dynamic range |  | 110 | 115 |  | dB | AVDD=5.0V; 60dBFS with A-weighted | 11 |
| S/N (A-weighted) |  | 110 | 115 |  | dB | AVDD=5.0V; A-weighted | 11 |
| Interchannel isolation |  | 100 | 110 |  | dB | AVDD=5.0V; 1kHz | 11 |
| Interchannel gain mismatch |  |  | 0 | 0.3 | dB | AVDD=5.0V | 11 |
| Output voltage |  | 2.65 | 2.8 | 2.95 | Vpp | AVDD=5.0V; 0dB, 1kHz sine (Note 13) | 11 |
| Load resistance |  | 2 |  |  | kΩ | AVDD=5.0V; AC load with DC cut capacitor (Note 14) | 11 |
| Load capacitance |  |  |  | 30 | pF | AVDD=5.0V (Note 14) | 11 |
| Power supply current, normal operation | AVDD |  | 31 | 41 | mA | AVDD=5.0V; PDN pin = H | 11 |
| Power supply current, normal operation (fs=44.1kHz) | TVDD |  | 8 | 11 | mA | AVDD=5.0V; PDN pin = H; fs=44.1kHz | 11 |
| Power supply current, normal operation (fs=96kHz) | TVDD |  | 13 | 17 | mA | AVDD=5.0V; PDN pin = H; fs=96kHz | 11 |
| Power supply current, normal operation (fs=192kHz) | TVDD |  | 20 | 26 | mA | AVDD=5.0V; PDN pin = H; fs=192kHz | 11 |
| Power-down current | AVDD+TVDD |  | 1 | 100 | µA | PDN pin = L (Note 15) | 11 |
| THD+N (0dBFS) | THD+N |  | -93 | -86 | dB | AVDD=3.3V; fs=44.1kHz; BW=20kHz; 0dBFS | 12 |
| Dynamic range |  | 106 | 111 |  | dB | AVDD=3.3V; 60dBFS with A-weighted | 12 |
| S/N (A-weighted) |  | 106 | 111 |  | dB | AVDD=3.3V; A-weighted | 12 |
| Interchannel isolation |  | 100 | 110 |  | dB | AVDD=3.3V; 1kHz | 12 |
| Interchannel gain mismatch |  |  | 0 | 0.3 | dB | AVDD=3.3V | 12 |
| Output voltage |  | 1.66 | 1.85 | 2.04 | Vpp | AVDD=3.3V; 0dB, 1kHz sine (Note 13) | 12 |
| Load resistance |  | 2 |  |  | kΩ | AVDD=3.3V; AC load with DC cut capacitor (Note 14) | 12 |
| Load capacitance |  |  |  | 30 | pF | AVDD=3.3V (Note 14) | 12 |
| High-level input voltage | VIH | 80 |  |  | %TVDD | TVDD=1.7 to 3.0V; Ta=-40 to 105°C | 21 |
| Low-level input voltage | VIL |  |  | 20 | %TVDD | TVDD=1.7 to 3.0V; Ta=-40 to 105°C | 21 |
| High-level input voltage | VIH | 70 |  |  | %TVDD | TVDD=3.0 to 3.6V; Ta=-40 to 105°C | 21 |
| Low-level input voltage | VIL |  |  | 30 | %TVDD | TVDD=3.0 to 3.6V; Ta=-40 to 105°C | 21 |
| Low-level output voltage | VOL |  |  | 0.5 | V | Except SDA pin; Iout=100µA | 21 |
| Low-level output voltage (SDA) | VOL |  |  | 0.4 | V | SDA pin, 2.0V≤TVDD≤3.6V; Iout=3mA | 21 |
| Low-level output voltage (SDA) | VOL |  |  | 20 | %TVDD | SDA pin, 1.7V≤TVDD≤2.0V; Iout=3mA | 21 |
| Input leakage current | Iin |  |  | 10 | µA |  | 21 |
| Master clock frequency | fCLK | 2.048 |  | 49.152 | MHz | Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF | 22 |
| Master clock duty cycle | dCLK | 40 |  | 60 | % | Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF | 22 |
| Master clock high pulse width | tCLKH | 9.155 |  |  | ns | Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF | 22 |
| Master clock low pulse width | tCLKL | 9.155 |  |  | ns | Ta=-40 to 105°C; AVDD=3.0 to 5.5V; TVDD=1.7 to 3.6V; CL=20pF | 22 |
| LRCK frequency, normal speed mode | fsn | 8 |  | 54 | kHz | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| LRCK frequency, double speed mode | fsd | 54 |  | 108 | kHz | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| LRCK frequency, quad speed mode | fsq | 108 |  | 216 | kHz | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| LRCK duty cycle | Duty | 45 |  | 55 | % | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| BICK pulse width low | tBCKL | 9 |  |  | nsec | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| BICK pulse width high | tBCKH | 9 |  |  | nsec | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| BICK to LRCK edge | tBLR | 5 |  |  | nsec | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| LRCK edge to BICK | tLRB | 5 |  |  | nsec | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| SDTI1/2/3/4 hold time | tSDH | 5 |  |  | nsec | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |
| SDTI1/2/3/4 setup time | tSDS | 5 |  |  | nsec | Normal Mode (TDM1-0 bits = 00); CL=20pF | 22 |

## CAD (KiCad official)

- Symbol: `AK4458VN`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: QFN-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `ak4458vn-etched.step` / `ak4458vn-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ak4458vn.step` / `ak4458vn.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Asahi Kasei Microdevices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589957139754999809) (90 pp, sha256 `1d837ff1e7301b22`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ak4458vn-datasheet.pdf)