# AK4454VN

**Asahi Kasei Microdevices** · Digital To Analog Converters (DACs) · QFN-32-EP(5x5)

AK4454VN from Asahi Kasei Microdevices, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MCLK | input | External master clock input pin (Hi-Z in power-down state). |
| 2 | BICK/DCLK | input | Audio serial data clock input in PCM mode (BICK) or DSD clock input in DSD mode (DCLK). |
| 3 | LRCK/DSDL1 | input | Input channel clock in PCM mode (LRCK) or audio serial data input in DSD mode (DSDL1). |
| 4 | SDTI1/DSDR1 | input | Audio serial data input in PCM mode (SDTI1) or in DSD mode (DSDR1); must be tied to DVSS if unused. |
| 5 | SDTI2/DSDL2 | input | Audio serial data input in PCM mode (SDTI2) or in DSD mode (DSDL2); must be tied to DVSS if unused. |
| 6 | DSDR2/TDMO1 | bidirectional | DSD audio serial data input (DSDR2) or audio serial data output in Daisy Chain mode (TDMO1), with 100kΩ pull-down in power-down state; TDMO1 must be open if unused. |
| 7 | DZF/SMUTE | bidirectional | Zero input detect output in I2C or 3-wire control mode (DZF), or soft mute input in Parallel control mode (SMUTE, H initiates soft mute); 100kΩ pull-down in power-down state, DZF must be open if unused. |
| 8 | CAD1/DCHAIN | input | Chip address pin in I2C or 3-wire serial control mode (CAD1), or Daisy Chain mode select in Parallel control mode (DCHAIN). |
| 9 | SDA/CDTI/TDM0 | bidirectional | Control data pin in I2C mode (SDA, I/O), control data input in 3-wire mode (CDTI), or TDM mode select in Parallel control mode (TDM0). |
| 10 | SCL/CCLK/TDM1 | input | Control data clock in I2C mode (SCL) or 3-wire mode (CCLK), or TDM mode select in Parallel control mode (TDM1). |
| 11 | CAD0_I2C/CSN/DIF | input | Chip address 0 in I2C mode (CAD0_I2C), chip select in 3-wire mode (CSN), or audio data format select in Parallel mode (DIF: L = 32-bit MSB, H = 32-bit I2S). |
| 12 | PS/CAD0_SPI | input | Control mode select when I2C pin = H (PS: L = I2C bus serial control, H = Parallel control), or chip address 0 in 3-wire mode when I2C pin = L (CAD0_SPI). |
| 13 | I2C | input | Control mode select pin: L = 3-wire serial control mode, H = I2C bus serial control mode or Parallel control mode. |
| 14 | AOUTL1P | output | L channel positive analog output 1 (Hi-Z in power-down); must be open if unused. |
| 15 | AOUTL1N | output | L channel negative analog output 1 (Hi-Z in power-down); must be open if unused. |
| 16 | VREFL1 | input | Negative voltage reference input pin for DAC1, connected to AVSS. |
| 17 | VREFH1 | input | Positive voltage reference input pin for DAC1, connected to AVDD (VREFH min AVDD-0.5V). |
| 18 | AOUTR1N | output | R channel negative analog output 1 (Hi-Z in power-down); must be open if unused. |
| 19 | AOUTR1P | output | R channel positive analog output 1 (Hi-Z in power-down); must be open if unused. |
| 20 | AVSS | power_in | Analog ground pin; must be connected to the same ground plane as DVSS. |
| 21 | AVDD | power_in | Analog power supply pin, 3.0V to 5.5V. |
| 22 | AOUTL2P | output | L channel positive analog output 2 (Hi-Z in power-down); must be open if unused. |
| 23 | AOUTL2N | output | L channel negative analog output 2 (Hi-Z in power-down); must be open if unused. |
| 24 | VREFH2 | input | Positive voltage reference input pin for DAC2, connected to AVDD (VREFH min AVDD-0.5V). |
| 25 | VREFL2 | input | Negative voltage reference input pin for DAC2, connected to AVSS. |
| 26 | AOUTR2N | output | R channel negative analog output 2 (Hi-Z in power-down); must be open if unused. |
| 27 | AOUTR2P | output | R channel positive analog output 2 (Hi-Z in power-down); must be open if unused. |
| 28 | LDOE | input | Internal LDO enable pin: L = disable, H = enable. |
| 29 | TVDD | power_in | Digital I/O power supply pin, 3.0V to 3.6V (1.7V to 3.6V per recommended operating conditions). |
| 30 | DVSS | power_in | Digital ground pin; must be connected to the same ground plane as AVSS. |
| 31 | VDD18 | bidirectional | LDO output pin when LDOE = H (connect to DVSS with 1.0µF), or 1.8V power input pin when LDOE = L (1.7V to 1.98V). |
| 32 | PDN | input | Power-down and reset pin; when L the device is powered down and control registers are reset to default. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | QFN-32-EP(5x5) |
| Category | Data Converters |
| Pins | 33 |

## CAD (KiCad official)

- Symbol: `AK4454VN`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `ak4454vn-etched.step` / `ak4454vn-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ak4454vn.step` / `ak4454vn.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Asahi Kasei Microdevices datasheet](docs/ak4454vn-datasheet.pdf) (88 pp, sha256 `116337ea1fe39b04`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ak4454vn-datasheet.pdf)