AiP74LVC2G08TA8.TR

{
  "slug": "aip74lvc2g08ta8-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "Wuxi I core Elec Logic Gates, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "aip74lvc2g08ta8.tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "aip74lvc2g08ta8-tr.kicad_sym",
    "aip74lvc2g08ta8-tr.kicad_mod",
    "aip74lvc2g08ta8-tr.glb",
    "aip74lvc2g08ta8-tr.step",
    "aip74lvc2g08ta8-tr.lbr",
    "docs/hero.png",
    "docs/aip74lvc2g08ta8-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "aip74lvc2g08ta8-tr-hero.glb",
    "aip74lvc2g08ta8-tr-hero.overlay.json",
    "aip74lvc2g08ta8-tr-etched.glb"
  ],
  "component": {
    "mpn": "AiP74LVC2G08TA8.TR",
    "manufacturer": "Wuxi I core Elec",
    "package": "TSSOP-8",
    "pin_count": 8,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590240049595260928",
    "parts": {
      "symbol": "aip74lvc2g08ta8-tr.kicad_sym",
      "footprint": "aip74lvc2g08ta8-tr.kicad_mod",
      "model_3d": "aip74lvc2g08ta8-tr-hero.glb",
      "model_3d_plain": "aip74lvc2g08ta8-tr-etched.glb",
      "model_3d_step": "aip74lvc2g08ta8-tr-etched.step",
      "model_3d_step_plain": "aip74lvc2g08ta8-tr.step",
      "lbr": "aip74lvc2g08ta8-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C5121353"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T20:41:20Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Data input A of gate 1; inputs accept voltages up to 5V and the recommended input voltage range is 0 to 5.5V."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Data input B of gate 1; inputs accept voltages up to 5V and the recommended input voltage range is 0 to 5.5V."
      },
      {
        "number": "3",
        "name": "2Y",
        "type": "output",
        "description": "Data output of gate 2; outputs are 5V tolerant for interfacing with 5V logic and provide ±24mA drive at VCC=3.0V."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground (0V); all voltages are referenced to this pin."
      },
      {
        "number": "5",
        "name": "2A",
        "type": "input",
        "description": "Data input A of gate 2; inputs accept voltages up to 5V and the recommended input voltage range is 0 to 5.5V."
      },
      {
        "number": "6",
        "name": "2B",
        "type": "input",
        "description": "Data input B of gate 2; inputs accept voltages up to 5V and the recommended input voltage range is 0 to 5.5V."
      },
      {
        "number": "7",
        "name": "1Y",
        "type": "output",
        "description": "Data output of gate 1; outputs are 5V tolerant for interfacing with 5V logic and provide ±24mA drive at VCC=3.0V."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage; recommended operating range is 1.65V to 5.5V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers and names come from the Pin Description table (section 2.3, page 3). The Pin Configurati; The TSSOP8 package outline drawing (section 5.1, page 10) is image-only in the extracted text, so no; Output pin descriptions combine the Features list (5V tolerant outputs, ±24mA at VCC=3.0V) with the "
        ],
        "pages_sent": 12,
        "cost_usd": 0.0508,
        "at": "2026-10-17T20:39:20"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590240049595260928",
        "pages": 12,
        "sha256": "8d3161627621d992",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "aip74lvc2g08ta8-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.9,
          3.0,
          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "cf28a51742b2e31065e201d1b313207140cbfb49062efd938788f7a310d02738",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "aip74lvc2g08ta8-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          4.9,
          3.0,
          1.1
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d51559cdea8c5b8680d5ee774790c2cfb7861554408540ef8e6cff761bc6942c",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}