component
AiP74LVC2G02TA8.TR
Public Made by Adomby adom
Wuxi I core Elec Logic Gates, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "aip74lvc2g02ta8-tr",
"version": "0.1.0",
"type": "component",
"description": "Wuxi I core Elec Logic Gates, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"logic",
"aip74lvc2g02ta8.tr",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"aip74lvc2g02ta8-tr.kicad_sym",
"aip74lvc2g02ta8-tr.kicad_mod",
"aip74lvc2g02ta8-tr.glb",
"aip74lvc2g02ta8-tr.step",
"aip74lvc2g02ta8-tr.lbr",
"docs/hero.png",
"docs/aip74lvc2g02ta8-tr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"aip74lvc2g02ta8-tr-hero.glb",
"aip74lvc2g02ta8-tr-hero.overlay.json",
"aip74lvc2g02ta8-tr-etched.glb"
],
"component": {
"mpn": "AiP74LVC2G02TA8.TR",
"manufacturer": "Wuxi I core Elec",
"package": "TSSOP-8",
"pin_count": 8,
"category": "Logic",
"subcategory": "Logic Gates",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602997905959763968",
"parts": {
"symbol": "aip74lvc2g02ta8-tr.kicad_sym",
"footprint": "aip74lvc2g02ta8-tr.kicad_mod",
"model_3d": "aip74lvc2g02ta8-tr-hero.glb",
"model_3d_plain": "aip74lvc2g02ta8-tr-etched.glb",
"model_3d_step": "aip74lvc2g02ta8-tr-etched.step",
"model_3d_step_plain": "aip74lvc2g02ta8-tr.step",
"lbr": "aip74lvc2g02ta8-tr.lbr"
},
"distributor_links": {
"lcsc": "C7425506"
},
"distributor_check": {
"checked_at": "2026-10-17T15:28:44Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "quota"
},
"mouser": {
"pn": null,
"status": "quota"
}
},
"pins": [
{
"number": "1",
"name": "1A",
"type": "input",
"description": "Data input 1A of gate 1 (NOR gate input); the datasheet states inputs accept voltages up to 5V and can be driven from 3.3V or 5V devices."
},
{
"number": "2",
"name": "1B",
"type": "input",
"description": "Data input 1B of gate 1 (NOR gate input); the datasheet states inputs accept voltages up to 5V and can be driven from 3.3V or 5V devices."
},
{
"number": "3",
"name": "2Y",
"type": "output",
"description": "Data output 2Y of gate 2, which is low when either 2A or 2B is high; the datasheet states outputs are 5V tolerant and rated ±24mA drive at VCC=3.0V."
},
{
"number": "4",
"name": "GND",
"type": "power_in",
"description": "Ground (0V) reference for all voltages in the datasheet."
},
{
"number": "5",
"name": "2A",
"type": "input",
"description": "Data input 2A of gate 2 (NOR gate input); the datasheet states inputs accept voltages up to 5V and can be driven from 3.3V or 5V devices."
},
{
"number": "6",
"name": "2B",
"type": "input",
"description": "Data input 2B of gate 2 (NOR gate input); the datasheet states inputs accept voltages up to 5V and can be driven from 3.3V or 5V devices."
},
{
"number": "7",
"name": "1Y",
"type": "output",
"description": "Data output 1Y of gate 1, which is low when either 1A or 1B is high; the datasheet states outputs are 5V tolerant and rated ±24mA drive at VCC=3.0V."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage, specified from 1.65V to 5.5V in the recommended operating conditions."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Section 2.2 'Pin Configurations' is a figure with no text in the extracted datasheet, so the pin num; The Pin Description table is shared by the TSSOP8 and VSSOP8 variants and does not name a package. T; Pin descriptions combine the Section 2.3 pin functions with limits from the general Features, Absolu"
],
"pages_sent": 12,
"cost_usd": 0.0497,
"at": "2026-10-17T15:26:44"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602997905959763968",
"pages": 12,
"sha256": "596635f584b96ed3",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "aip74lvc2g02ta8-tr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4.9,
3.0,
1.1
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "cf28a51742b2e31065e201d1b313207140cbfb49062efd938788f7a310d02738",
"checked": "2026-10-17",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "aip74lvc2g02ta8-tr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4.9,
3.0,
1.1
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "dc4bcef8808a6fbb50dc51c0a4fad2380a7b40670fc0171248bb86d7e80486a5",
"checked": "2026-10-17",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}