AiP74LVC1G123YA8.TR

{
  "slug": "aip74lvc1g123ya8-tr",
  "version": "0.1.0",
  "type": "component",
  "description": "Wuxi I core Elec Buffers, Drivers, Receivers, Transceivers, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "aip74lvc1g123ya8.tr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "aip74lvc1g123ya8-tr.kicad_sym",
    "aip74lvc1g123ya8-tr.kicad_mod",
    "aip74lvc1g123ya8-tr.glb",
    "aip74lvc1g123ya8-tr.step",
    "aip74lvc1g123ya8-tr.lbr",
    "docs/hero.png",
    "docs/aip74lvc1g123ya8-tr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "aip74lvc1g123ya8-tr-hero.glb",
    "aip74lvc1g123ya8-tr-hero.overlay.json",
    "aip74lvc1g123ya8-tr-etched.glb"
  ],
  "component": {
    "mpn": "AiP74LVC1G123YA8.TR",
    "manufacturer": "Wuxi I core Elec",
    "package": "VSSOP-8",
    "pin_count": 8,
    "category": "Logic",
    "subcategory": "Buffers, Drivers, Receivers, Transceivers",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602997907075719168",
    "parts": {
      "symbol": "aip74lvc1g123ya8-tr.kicad_sym",
      "footprint": "aip74lvc1g123ya8-tr.kicad_mod",
      "model_3d": "aip74lvc1g123ya8-tr-hero.glb",
      "model_3d_plain": "aip74lvc1g123ya8-tr-etched.glb",
      "model_3d_step": "aip74lvc1g123ya8-tr-etched.step",
      "model_3d_step_plain": "aip74lvc1g123ya8-tr.step",
      "lbr": "aip74lvc1g123ya8-tr.lbr"
    },
    "distributor_links": {
      "lcsc": "C7425508"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T11:19:52Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "A",
        "type": "input",
        "description": "Falling-edge trigger input; the datasheet specifies input voltage range 0 to 5.5 V and Schmitt-trigger inputs."
      },
      {
        "number": "2",
        "name": "B",
        "type": "input",
        "description": "Rising-edge trigger input; the datasheet specifies input voltage range 0 to 5.5 V and Schmitt-trigger inputs."
      },
      {
        "number": "3",
        "name": "CLR",
        "type": "input",
        "description": "Active-low reset and rising-edge trigger input; the datasheet specifies input voltage range 0 to 5.5 V and Schmitt-trigger inputs."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V)."
      },
      {
        "number": "5",
        "name": "Q",
        "type": "output",
        "description": "Non-inverted output; the datasheet rates the output drive at ±24 mA at VCC = 3.0 V."
      },
      {
        "number": "6",
        "name": "CEXT",
        "type": "passive",
        "description": "External timing capacitor connection; used with REXT/CEXT to set the base output pulse width."
      },
      {
        "number": "7",
        "name": "REXT/CEXT",
        "type": "passive",
        "description": "External timing resistor and capacitor connection; REXT must be at least 1 kΩ for VCC ≥ 3.0 V and at least 5 kΩ for VCC = 2.0 V."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage, recommended range 1.65 V to 5.5 V."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin 6 (CEXT) and pin 7 (REXT/CEXT) are external timing component connections; the datasheet does not; The pin table is shared by the TSSOP8 and VSSOP8 packages (and the datasheet's ordering table lists "
        ],
        "pages_sent": 22,
        "cost_usd": 0.0146,
        "at": "2026-10-18T11:18:04"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602997907075719168",
        "pages": 22,
        "sha256": "d93024ff3fb1a2df",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "aip74lvc1g123ya8-tr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.1,
          2.0,
          0.85
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "aip74lvc1g123ya8-tr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.1,
          2.0,
          0.85
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "6adf14cc6e9be1403f7441acd454d1b40a5a6a7ebff9b3452a8b867d291b70c8",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}