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AIP74LVC1G02GB235.TR
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Wuxi I core Elec Logic Gates, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AIP74LVC1G02GB235.TR
Wuxi I core Elec · Logic Gates · SOT-23-5
AIP74LVC1G02GB235.TR from Wuxi I core Elec, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B of the 2-input NOR gate; the datasheet recommends an input voltage range of 0 V to 5.5 V. |
| 2 | A | input | Data input A of the 2-input NOR gate; the datasheet recommends an input voltage range of 0 V to 5.5 V. |
| 3 | GND | power_in | Ground reference (0 V) for the device. |
| 4 | Y | output | Data output of the NOR gate; in operating mode the output voltage is limited to 0 V to VCC, and in power-down mode (VCC = 0 V) it may be up to 5.5 V. |
| 5 | VCC | power_in | Supply voltage; the recommended range is 1.65 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOT-23-5 |
| Category | Logic |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 6.5 | V | 4 | ||
| Input clamp current | IIK | -50 | mA | VI<0V | 4 | ||
| Input voltage | VI | -0.5 | 6.5 | V | 4 | ||
| Output clamp current | IOK | -50 | 50 | mA | VO>VCC or VO<0V | 4 | |
| Output voltage, operating mode | VO | -0.5 | V | operating mode; max printed as VCC+0.5 | 4 | ||
| Output voltage, power-down mode | VO | -0.5 | 6.5 | V | power-down mode | 4 | |
| Output current | IO | -50 | 50 | mA | VO=0V~VCC | 4 | |
| Supply current | ICC | 100 | mA | 4 | |||
| Ground current | IGND | -100 | mA | 4 | |||
| Total power dissipation | Ptot | 250 | mW | 4 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 4 | ||
| Soldering temperature | TL | 250 | ℃ | 10 秒 | 4 | ||
| Supply voltage | VCC | 1.65 | 5.5 | V | 4 | ||
| Input voltage | VI | 0 | 5.5 | V | 4 | ||
| Output voltage, working mode | VO | 0 | V | working mode; max printed as VCC | 4 | ||
| Output voltage, power-down mode | VO | 0 | 5.5 | V | power-down mode; VCC=0V | 4 | |
| Operating ambient temperature | Tamb | -40 | 105 | ℃ | 4 | ||
| Input rise and fall rate | Δt/ΔV | 20 | ns/V | VCC=1.65V~2.7V | 4 | ||
| Input rise and fall rate | Δt/ΔV | 10 | ns/V | VCC=2.7V~5.5V | 4 | ||
| High-level input voltage | VIH | 1.7 | V | VCC=2.3V |
6 | ||
| High-level input voltage | VIH | 2 | V | VCC=2.7V |
6 | ||
| Low-level input voltage | VIL | 0.7 | V | VCC=2.3V |
6 | ||
| Low-level input voltage | VIL | 0.8 | V | VCC=2.7V |
6 | ||
| High-level output voltage | VOH | 0.95 | V | IO=-4mA; VCC=1.65V; Tamb=-40~+105℃ | 6 | ||
| High-level output voltage | VOH | 1.7 | V | IO=-8mA; VCC=2.3V; Tamb=-40~+105℃ | 6 | ||
| High-level output voltage | VOH | 1.9 | V | IO=-12mA; VCC=2.7V; Tamb=-40~+105℃ | 6 | ||
| High-level output voltage | VOH | 2 | V | IO=-24mA; VCC=3.0V; Tamb=-40~+105℃ | 6 | ||
| High-level output voltage | VOH | 3.4 | V | IO=-32mA; VCC=4.5V; Tamb=-40~+105℃ | 6 | ||
| Low-level output voltage | VOL | 0.1 | V | IO=100uA; VCC=1.65V |
6 | ||
| Low-level output voltage | VOL | 0.7 | V | IO=4mA; VCC=1.65V; Tamb=-40~+105℃ | 6 | ||
| Low-level output voltage | VOL | 0.45 | V | IO=8mA; VCC=2.3V; Tamb=-40~+105℃ | 6 | ||
| Low-level output voltage | VOL | 0.6 | V | IO=12mA; VCC=2.7V; Tamb=-40~+105℃ | 6 | ||
| Low-level output voltage | VOL | 0.8 | V | IO=24mA; VCC=3.0V; Tamb=-40~+105℃ | 6 | ||
| Input leakage current | II | -1 | 1 | uA | VI=5.5V or GND; VCC=0V |
6 | |
| Power-off leakage current | IOFF | -2 | 2 | uA | VI or VO=5.5V; VCC=0V; Tamb=-40~+105℃ | 6 | |
| Quiescent supply current | ICC | 4 | uA | VI=5.5V or GND; IO=0A; VCC=1.65V |
6 | ||
| Additional quiescent supply current per input pin | ΔICC | 500 | uA | each pin; VI=VCC-0.6V; IO=0A; VCC=2.3V |
6 | ||
| Propagation delay A, B to Y | tpd | 1 | 10.5 | ns | see Fig. 5; VCC=1.65V |
7 | |
| Propagation delay A, B to Y | tpd | 0.5 | 7 | ns | see Fig. 5; VCC=2.3V |
7 | |
| Propagation delay A, B to Y | tpd | 0.5 | 6 | ns | see Fig. 5; VCC=3.0V |
7 | |
| Propagation delay A, B to Y | tpd | 0.5 | 5.5 | ns | see Fig. 5; VCC=4.5V |
7 | |
| Input capacitance | CI | 5 | pF | VCC=3.3V; VI=GND~VCC | 5 | ||
| Power dissipation capacitance | CPD | 14 | pF | VCC=3.3V; VI=GND~VCC | 7 |
CAD (KiCad official)
- Symbol:
AIP74LVC1G02GB235.TR - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
aip74lvc1g02gb235-tr-etched.step/aip74lvc1g02gb235-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74lvc1g02gb235-tr.step/aip74lvc1g02gb235-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (12 pp, sha256
2fb7e312ddc500d2, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AIP74LVC1G02GB235.TR
**Wuxi I core Elec** · Logic Gates · SOT-23-5
AIP74LVC1G02GB235.TR from Wuxi I core Elec, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | B | input | Data input B of the 2-input NOR gate; the datasheet recommends an input voltage range of 0 V to 5.5 V. |
| 2 | A | input | Data input A of the 2-input NOR gate; the datasheet recommends an input voltage range of 0 V to 5.5 V. |
| 3 | GND | power_in | Ground reference (0 V) for the device. |
| 4 | Y | output | Data output of the NOR gate; in operating mode the output voltage is limited to 0 V to VCC, and in power-down mode (VCC = 0 V) it may be up to 5.5 V. |
| 5 | VCC | power_in | Supply voltage; the recommended range is 1.65 V to 5.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOT-23-5 |
| Category | Logic |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 6.5 | V | | 4 |
| Input clamp current | IIK | -50 | | | mA | VI<0V | 4 |
| Input voltage | VI | -0.5 | | 6.5 | V | | 4 |
| Output clamp current | IOK | -50 | | 50 | mA | VO>VCC or VO<0V | 4 |
| Output voltage, operating mode | VO | -0.5 | | | V | operating mode; max printed as VCC+0.5 | 4 |
| Output voltage, power-down mode | VO | -0.5 | | 6.5 | V | power-down mode | 4 |
| Output current | IO | -50 | | 50 | mA | VO=0V~VCC | 4 |
| Supply current | ICC | | | 100 | mA | | 4 |
| Ground current | IGND | -100 | | | mA | | 4 |
| Total power dissipation | Ptot | | | 250 | mW | | 4 |
| Storage temperature | Tstg | -65 | | 150 | ℃ | | 4 |
| Soldering temperature | TL | | | 250 | ℃ | 10 秒 | 4 |
| Supply voltage | VCC | 1.65 | | 5.5 | V | | 4 |
| Input voltage | VI | 0 | | 5.5 | V | | 4 |
| Output voltage, working mode | VO | 0 | | | V | working mode; max printed as VCC | 4 |
| Output voltage, power-down mode | VO | 0 | | 5.5 | V | power-down mode; VCC=0V | 4 |
| Operating ambient temperature | Tamb | -40 | | 105 | ℃ | | 4 |
| Input rise and fall rate | Δt/ΔV | | | 20 | ns/V | VCC=1.65V~2.7V | 4 |
| Input rise and fall rate | Δt/ΔV | | | 10 | ns/V | VCC=2.7V~5.5V | 4 |
| High-level input voltage | VIH | 1.7 | | | V | VCC=2.3V~2.7V; Tamb=-40~+105℃ | 6 |
| High-level input voltage | VIH | 2 | | | V | VCC=2.7V~3.6V; Tamb=-40~+105℃ | 6 |
| Low-level input voltage | VIL | | | 0.7 | V | VCC=2.3V~2.7V; Tamb=-40~+105℃ | 6 |
| Low-level input voltage | VIL | | | 0.8 | V | VCC=2.7V~3.6V; Tamb=-40~+105℃ | 6 |
| High-level output voltage | VOH | 0.95 | | | V | IO=-4mA; VCC=1.65V; Tamb=-40~+105℃ | 6 |
| High-level output voltage | VOH | 1.7 | | | V | IO=-8mA; VCC=2.3V; Tamb=-40~+105℃ | 6 |
| High-level output voltage | VOH | 1.9 | | | V | IO=-12mA; VCC=2.7V; Tamb=-40~+105℃ | 6 |
| High-level output voltage | VOH | 2 | | | V | IO=-24mA; VCC=3.0V; Tamb=-40~+105℃ | 6 |
| High-level output voltage | VOH | 3.4 | | | V | IO=-32mA; VCC=4.5V; Tamb=-40~+105℃ | 6 |
| Low-level output voltage | VOL | | | 0.1 | V | IO=100uA; VCC=1.65V~5.5V; Tamb=-40~+105℃ | 6 |
| Low-level output voltage | VOL | | | 0.7 | V | IO=4mA; VCC=1.65V; Tamb=-40~+105℃ | 6 |
| Low-level output voltage | VOL | | | 0.45 | V | IO=8mA; VCC=2.3V; Tamb=-40~+105℃ | 6 |
| Low-level output voltage | VOL | | | 0.6 | V | IO=12mA; VCC=2.7V; Tamb=-40~+105℃ | 6 |
| Low-level output voltage | VOL | | | 0.8 | V | IO=24mA; VCC=3.0V; Tamb=-40~+105℃ | 6 |
| Input leakage current | II | -1 | | 1 | uA | VI=5.5V or GND; VCC=0V~5.5V; Tamb=-40~+105℃ | 6 |
| Power-off leakage current | IOFF | -2 | | 2 | uA | VI or VO=5.5V; VCC=0V; Tamb=-40~+105℃ | 6 |
| Quiescent supply current | ICC | | | 4 | uA | VI=5.5V or GND; IO=0A; VCC=1.65V~5.5V; Tamb=-40~+105℃ | 6 |
| Additional quiescent supply current per input pin | ΔICC | | | 500 | uA | each pin; VI=VCC-0.6V; IO=0A; VCC=2.3V~5.5V; Tamb=-40~+105℃ | 6 |
| Propagation delay A, B to Y | tpd | 1 | | 10.5 | ns | see Fig. 5; VCC=1.65V~1.95V; Tamb=-40~+105℃ | 7 |
| Propagation delay A, B to Y | tpd | 0.5 | | 7 | ns | see Fig. 5; VCC=2.3V~2.7V; Tamb=-40~+105℃ | 7 |
| Propagation delay A, B to Y | tpd | 0.5 | | 6 | ns | see Fig. 5; VCC=3.0V~3.6V; Tamb=-40~+105℃ | 7 |
| Propagation delay A, B to Y | tpd | 0.5 | | 5.5 | ns | see Fig. 5; VCC=4.5V~5.5V; Tamb=-40~+105℃ | 7 |
| Input capacitance | CI | | 5 | | pF | VCC=3.3V; VI=GND~VCC | 5 |
| Power dissipation capacitance | CPD | | 14 | | pF | VCC=3.3V; VI=GND~VCC | 7 |
## CAD (KiCad official)
- Symbol: `AIP74LVC1G02GB235.TR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `aip74lvc1g02gb235-tr-etched.step` / `aip74lvc1g02gb235-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aip74lvc1g02gb235-tr.step` / `aip74lvc1g02gb235-tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Wuxi I core Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590902930449256448) (12 pp, sha256 `2fb7e312ddc500d2`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/aip74lvc1g02gb235-tr-datasheet.pdf)