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AIP74HCT244SA.TB

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Wuxi I-core Elec Buffer/Driver/Transceiver, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AIP74HCT244SA.TB

Wuxi I-core Elec · Buffer/Driver/Transceiver · SOP-20-300mil

AIP74HCT244SA.TB from Wuxi I-core Elec, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Active-LOW output enable input for the 1Y0-1Y3 outputs; a HIGH puts them in high-impedance OFF-state.
2 1A0 input Data input 0 of the first 4-bit buffer, with TTL-level thresholds on the HCT244 (VIH 2.0 V min, VIL 0.8 V max).
3 2Y0 tri_state 3-state bus output 0 of the second 4-bit buffer, high-impedance when 2OE is HIGH.
4 1A1 input Data input 1 of the first 4-bit buffer, with TTL-level thresholds on the HCT244.
5 2Y1 tri_state 3-state bus output 1 of the second 4-bit buffer, high-impedance when 2OE is HIGH.
6 1A2 input Data input 2 of the first 4-bit buffer, with TTL-level thresholds on the HCT244.
7 2Y2 tri_state 3-state bus output 2 of the second 4-bit buffer, high-impedance when 2OE is HIGH.
8 1A3 input Data input 3 of the first 4-bit buffer, with TTL-level thresholds on the HCT244.
9 2Y3 tri_state 3-state bus output 3 of the second 4-bit buffer, high-impedance when 2OE is HIGH.
10 GND power_in Ground (0 V).
11 2A3 input Data input 3 of the second 4-bit buffer, with TTL-level thresholds on the HCT244.
12 1Y3 tri_state 3-state bus output 3 of the first 4-bit buffer, high-impedance when 1OE is HIGH.
13 2A2 input Data input 2 of the second 4-bit buffer, with TTL-level thresholds on the HCT244.
14 1Y2 tri_state 3-state bus output 2 of the first 4-bit buffer, high-impedance when 1OE is HIGH.
15 2A1 input Data input 1 of the second 4-bit buffer, with TTL-level thresholds on the HCT244.
16 1Y1 tri_state 3-state bus output 1 of the first 4-bit buffer, high-impedance when 1OE is HIGH.
17 2A0 input Data input 0 of the second 4-bit buffer, with TTL-level thresholds on the HCT244.
18 1Y0 tri_state 3-state bus output 0 of the first 4-bit buffer, high-impedance when 1OE is HIGH.
19 2OE input Active-LOW output enable input for the 2Y0-2Y3 outputs; a HIGH puts them in high-impedance OFF-state.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended for AiP74HCT244 (absolute maximum -0.5 V to +7.0 V).

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package SOP-20-300mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 6
Input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 6
Output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 6
Output current IO -35 35 mA -0.5V < VO < VCC+0.5V 6
Supply current ICC 70 mA 6
Ground current IGND -70 mA 6
Storage temperature Tstg -65 150 ℃ 6
Total power dissipation Ptot 500 mW SOP20: above 70℃ derates linearly with 8mW/K 6
Soldering temperature TL 250 ℃ 10s, SOP 6
Supply voltage VCC 4.5 5 5.5 V 6
Input voltage VI 0 V max printed as VCC 6
Output voltage VO 0 V max printed as VCC 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 6
Ambient temperature Tamb -40 85 ℃ 6
HIGH-level input voltage VIH 2 1.6 V Tamb=25℃; VCC=4.5V to 5.5V 7
LOW-level input voltage VIL 1.2 0.8 V Tamb=25℃; VCC=4.5V to 5.5V 7
HIGH-level output voltage VOH 4.4 4.5 V Tamb=25℃; VI = VIH or VIL; VCC=4.5V; IO=-20uA 7
HIGH-level output voltage VOH 3.98 4.32 V Tamb=25℃; VI = VIH or VIL; VCC=4.5V; IO=-6.0mA 7
LOW-level output voltage VOL 0 0.1 V Tamb=25℃; VI = VIH or VIL; VCC=4.5V; IO=20uA 7
LOW-level output voltage VOL 0.16 0.26 V Tamb=25℃; VI = VIH or VIL; VCC=4.5V; IO=6.0mA 7
Input leakage current II -0.1 0.1 uA Tamb=25℃; VI=VCC or GND; VCC=5.5V 7
OFF-state output current IOZ -0.5 0.5 uA Tamb=25℃; VI=VIH or VIL; VCC=5.5V; VO=VCC or GND 7
Supply current ICC 8 uA Tamb=25℃; VI=VCC or GND; IO=0A; VCC=5.5V 7
Additional supply current ΔICC 70 252 uA Tamb=25℃; per input pin; VI=VCC-2.1V; other inputs at VCC or GND; VCC=4.5V to 5.5V; IO=0A 7
Input capacitance CI 3.5 pF Tamb=25℃ 7
HIGH-level input voltage VIH 2 V Tamb=-40℃ to +85℃; VCC=4.5V to 5.5V 8
LOW-level input voltage VIL 0.8 V Tamb=-40℃ to +85℃; VCC=4.5V to 5.5V 8
HIGH-level output voltage VOH 4.4 V Tamb=-40℃ to +85℃; VI = VIH or VIL; VCC=4.5V; IO=-20uA 8
HIGH-level output voltage VOH 3.84 V Tamb=-40℃ to +85℃; VI = VIH or VIL; VCC=4.5V; IO=-6.0mA 8
LOW-level output voltage VOL 0.1 V Tamb=-40℃ to +85℃; VI = VIH or VIL; VCC=4.5V; IO=20uA 8
LOW-level output voltage VOL 0.33 V Tamb=-40℃ to +85℃; VI = VIH or VIL; VCC=4.5V; IO=6.0mA 8
Input leakage current II -1 1 uA Tamb=-40℃ to +85℃; VI=VCC or GND; VCC=5.5V 8
OFF-state output current IOZ -5 5 uA Tamb=-40℃ to +85℃; VI=VIH or VIL; VCC=5.5V; VO=VCC or GND 8
Supply current ICC 80 uA Tamb=-40℃ to +85℃; VI=VCC or GND; IO=0A; VCC=5.5V 8
Additional supply current ΔICC 315 uA Tamb=-40℃ to +85℃; per input pin; VI=VCC-2.1V; other inputs at VCC or GND; VCC=4.5V to 5.5V; IO=0A 8
Propagation delay nAn to nYn tpd 13 22 ns Tamb=25℃; VCC=4.5V; see Figure 5 9
Propagation delay nAn to nYn tpd 11 ns Tamb=25℃; VCC=5.0V; CL=15pF 9
Enable time nOE to nYn ten 15 30 ns Tamb=25℃; VCC=4.5V; see Figure 6 9
Disable time nOE to nYn tdis 15 25 ns Tamb=25℃; VCC=4.5V; see Figure 6 9
Transition time tt 5 12 ns Tamb=25℃; VCC=4.5V; see Figure 5 9
Power dissipation capacitance CPD 35 pF Tamb=25℃; per buffer; VI=GND to VCC-1.5V 9
Propagation delay nAn to nYn tpd 22 ns Tamb=-40℃ to +85℃; see Figure 5 10
Enable time nOE to nYn ten 30 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 10
Disable time nOE to nYn tdis 25 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 10
Transition time tt 12 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 5 10

CAD (KiCad official)

  • Symbol: AIP74HCT244SA.TB
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: aip74hct244sa-tb-etched.step / aip74hct244sa-tb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hct244sa-tb.step / aip74hct244sa-tb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (16 pp, sha256 06f00ce8e30be55b, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF