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AiP74HC595TA16.TR
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Wuxi I core Elec Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAiP74HC595TA16.TR
Wuxi I core Elec · Shift Registers · TSSOP-16
AiP74HC595TA16.TR from Wuxi I core Elec, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | tri_state | Parallel data output stage 1 from 8-bit storage register; tri-state output controlled by OE-. |
| 2 | Q2 | tri_state | Parallel data output stage 2 from 8-bit storage register; tri-state output controlled by OE-. |
| 3 | Q3 | tri_state | Parallel data output stage 3 from 8-bit storage register; tri-state output controlled by OE-. |
| 4 | Q4 | tri_state | Parallel data output stage 4 from 8-bit storage register; tri-state output controlled by OE-. |
| 5 | Q5 | tri_state | Parallel data output stage 5 from 8-bit storage register; tri-state output controlled by OE-. |
| 6 | Q6 | tri_state | Parallel data output stage 6 from 8-bit storage register; tri-state output controlled by OE-. |
| 7 | Q7 | tri_state | Parallel data output stage 7 from 8-bit storage register; tri-state output controlled by OE-. |
| 8 | GND | power_in | Ground reference (0V). |
| 9 | Q7S | output | Serial data output from stage 7 of shift register for cascading; unaffected by OE-. |
| 10 | MR, | input | Master reset input (active low); low level resets shift register. |
| 11 | SHCP | input | Shift register clock input; data shifts into stage 0 on rising edge. |
| 12 | STCP | input | Storage register clock input; data transfers from shift register to storage register on rising edge. |
| 13 | OE, | input | Output enable input (active low); low enables tri-state outputs Q0-Q7, high causes high-impedance state. |
| 14 | DS | input | Serial data input to stage 0 of shift register. |
| 15 | Q0 | tri_state | Parallel data output stage 0 from 8-bit storage register; tri-state output controlled by OE-. |
| 16 | VCC | power_in | Positive power supply voltage; recommended operating range 2.0V to 6.0V for AiP74HC595. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
AiP74HC595TA16.TR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
aip74hc595ta16-tr-etched.step/aip74hc595ta16-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc595ta16-tr.step/aip74hc595ta16-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (24 pp, sha256
095dd5a11460e6c7, retrieved 2026-09-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).