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AIP74HC595SA.TR

Public Made by Adom

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Wuxi I-core Elec Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AIP74HC595SA.TR

Wuxi I-core Elec · Registers · SOP-16

AIP74HC595SA.TR from Wuxi I-core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output 1 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
2 Q2 tri_state Parallel data output 2 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
3 Q3 tri_state Parallel data output 3 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
4 Q4 tri_state Parallel data output 4 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
5 Q5 tri_state Parallel data output 5 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
6 Q6 tri_state Parallel data output 6 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
7 Q7 tri_state Parallel data output 7 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
8 GND power_in Ground (0V) reference for all voltages.
9 Q7S output Serial data output for cascading; drives 4.0mA at VCC=4.5V, absolute max output current ±25mA.
10 MR input Master reset, active LOW; a LOW asynchronously clears the shift register only.
11 SHCP input Shift register clock input; data shifts on the LOW-to-HIGH transition.
12 STCP input Storage register clock input; shift register data is transferred to the storage register on the LOW-to-HIGH transition.
13 OE input Output enable input, active LOW; HIGH puts Qn outputs in high-impedance OFF-state without affecting register state.
14 DS input Serial data input to the shift register.
15 Q0 tri_state Parallel data output 0 (3-state); bus driver output sourcing/sinking 6.0mA at VCC=4.5V.
16 VCC power_in Supply voltage, 2.0V to 6.0V for AiP74HC595 (absolute max 7.0V).

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package SOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 7
Input clamping current IIK 20 mA VI < -0.5V or VI > VCC+0.5V; printed ±20 7
Output clamping current IOK 20 mA VO < -0.5V or VO > VCC+0.5V; printed ±20 7
Output current pin Q7S IO 25 mA VO= -0.5V to (VCC+0.5V); pin Q7S; printed ±25 7
Output current pins Qn IO 35 mA VO= -0.5V to (VCC+0.5V); pins Qn; printed ±35 7
Supply current ICC 70 mA 7
Ground current IGND -70 mA 7
Storage temperature Tstg -65 150 ℃ 7
Total power dissipation Ptot 500 mW 7
Soldering temperature SOP TL 250 ℃ 10s; SOP 7
Supply voltage VCC 2 5 6 V AiP74HC595 8
Input voltage VI 0 6 V 0 to VCC; AiP74HC595 8
Output voltage VO 0 6 V 0 to VCC; AiP74HC595 8
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 8
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 8
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 8
Ambient temperature Tamb -40 85 ℃ 8
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V 8
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V 8
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V 8
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V 8
LOW-level input voltage VIL 2.1 1.35 V VCC=4.5V 8
LOW-level input voltage VIL 2.8 1.8 V VCC=6.0V 8
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; all outputs; IO=-20uA; VCC=2.0V 8
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; all outputs; IO=-20uA; VCC=4.5V 8
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; all outputs; IO=-20uA; VCC=6.0V 8
HIGH-level output voltage Q7S VOH 3.84 4.32 V VI = VIH or VIL; Q7S output; IO=-4.0mA; VCC=4.5V 8
HIGH-level output voltage Q7S VOH 5.34 5.81 V VI = VIH or VIL; Q7S output; IO=-5.2mA; VCC=6.0V 8
HIGH-level output voltage Qn VOH 3.84 4.32 V VI = VIH or VIL; Qn bus driver outputs; IO=-6.0mA; VCC=4.5V 8
HIGH-level output voltage Qn VOH 5.34 5.81 V VI = VIH or VIL; Qn bus driver outputs; IO=-7.8mA; VCC=6.0V 8
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; all outputs; IO=20uA; VCC=2.0V 9
LOW-level output voltage Q7S VOL 0.15 0.33 V VI = VIH or VIL; Q7S output; IO=4.0mA; VCC=4.5V 9
LOW-level output voltage Q7S VOL 0.16 0.33 V VI = VIH or VIL; Q7S output; IO=5.2mA; VCC=6.0V 9
LOW-level output voltage Qn VOL 0.15 0.33 V VI = VIH or VIL; Qn bus driver outputs; IO=6.0mA; VCC=4.5V 9
LOW-level output voltage Qn VOL 0.16 0.33 V VI = VIH or VIL; Qn bus driver outputs; IO=7.8mA; VCC=6.0V 9
Input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V 9
OFF-state output current IOZ -5 5 uA VI=VIH or VIL; VCC=6.0V; VO=VCC or GND 9
Supply current ICC 80 uA VI=VCC or GND; IO=0A; VCC=6.0V 9
Input capacitance CI 3.5 pF 9
Propagation delay SHCP to Q7S tpd 19 32 ns Tamb=25℃; VCC=4.5V; see Figure 6 10
Propagation delay STCP to Qn tpd 20 35 ns Tamb=25℃; VCC=4.5V; see Figure 7 10
HIGH to LOW propagation delay MR to Q7S tPHL 17 35 ns Tamb=25℃; VCC=4.5V; see Figure 9 10
OE to Qn enable time ten 17 30 ns Tamb=25℃; VCC=4.5V; see Figure 10 10
OE to Qn disable time tdis 15 30 ns Tamb=25℃; VCC=4.5V; see Figure 10 10
Pulse width SHCP HIGH or LOW tW 15 6 ns Tamb=25℃; VCC=4.5V; see Figure 6 10
Set-up time DS to SHCP tsu 10 4 ns Tamb=25℃; VCC=4.5V; see Figure 8 10
Hold time DS to SHCP th 3 -2 ns Tamb=25℃; VCC=4.5V; see Figure 8 10
Recovery time MR to SHCP trec 10 -7 ns Tamb=25℃; VCC=4.5V; see Figure 9 10
Maximum frequency fmax 30 91 MHz Tamb=25℃; SHCP or STCP; VCC=4.5V; see Figure 6 and Figure 7 10
Power dissipation capacitance CPD 115 pF Tamb=25℃; all 9 outputs switching; fi=1MHz; VI=GND to VCC 10
Propagation delay SHCP to Q7S tpd 40 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 12
Propagation delay STCP to Qn tpd 44 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 12
HIGH to LOW propagation delay MR to Q7S tPHL 44 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 9 12
OE to Qn enable time ten 38 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 10 12
Maximum frequency fmax 24 MHz Tamb=-40℃ to +85℃; SHCP or STCP; VCC=4.5V; see Figure 6 and Figure 7 12

CAD (KiCad official)

  • Symbol: AIP74HC595SA.TR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: aip74hc595sa-tr-etched.step / aip74hc595sa-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc595sa-tr.step / aip74hc595sa-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (20 pp, sha256 98279ca4758badb0, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF