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AIP74HC574TA.TR

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Wuxi I-core Elec Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AIP74HC574TA.TR

Wuxi I-core Elec · Flip Flops · TSSOP-20

AIP74HC574TA.TR from Wuxi I-core Elec, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low 3-state output enable; a HIGH level forces all Q outputs to high impedance, and changes on OE do not affect the flip-flop state.
2 D0 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
3 D1 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
4 D2 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
5 D3 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
6 D4 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
7 D5 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
8 D6 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
9 D7 input Data input sampled on the rising edge of CP, with internal clamp diodes that allow voltages above VCC through a series current-limiting resistor.
10 GND power_in Ground reference (0 V).
11 CP input Clock input; the D inputs are loaded into the flip-flops on the rising edge.
12 Q7 tri_state 3-state output of flip-flop 7, high impedance while OE is HIGH.
13 Q6 tri_state 3-state output of flip-flop 6, high impedance while OE is HIGH.
14 Q5 tri_state 3-state output of flip-flop 5, high impedance while OE is HIGH.
15 Q4 tri_state 3-state output of flip-flop 4, high impedance while OE is HIGH.
16 Q3 tri_state 3-state output of flip-flop 3, high impedance while OE is HIGH.
17 Q2 tri_state 3-state output of flip-flop 2, high impedance while OE is HIGH.
18 Q1 tri_state 3-state output of flip-flop 1, high impedance while OE is HIGH.
19 Q0 tri_state 3-state output of flip-flop 0, high impedance while OE is HIGH.
20 VCC power_in Supply voltage; recommended 2.0 V to 6.0 V for the HC variant and 4.5 V to 5.5 V for the HCT variant, absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 6
Input clamp current IIK -20 20 mA VI<-0.5V or VI>VCC+0.5V 6
Output clamp current IOK -20 20 mA VO<-0.5V or VO>VCC+0.5V 6
Output current IO -35 35 mA -0.5V<VO<VCC+0.5V 6
Supply current ICC 70 mA 6
Ground current IGND -70 mA 6
Storage temperature Tstg -65 150 °C 6
Total power dissipation Ptot 500 mW 6
Supply voltage VCC 2 5 6 V AiP74HC574 7
Operating ambient temperature Tamb -40 85 °C AiP74HC574 7
Input rise and fall slew rate Δt/ΔV 625 ns/V VCC=2.0V 7
Input rise and fall slew rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 7
Input rise and fall slew rate Δt/ΔV 83 ns/V VCC=6.0V 7
High-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40~+85℃ 8
High-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40~+85℃ 8
High-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40~+85℃ 8
Low-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40~+85℃ 8
Low-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40~+85℃ 8
Low-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40~+85℃ 8
High-level output voltage VOH 1.9 V VI=VIH or VIL; IO=-20uA; VCC=2.0V; Tamb=-40~+85℃ 8
High-level output voltage VOH 4.4 V VI=VIH or VIL; IO=-20uA; VCC=4.5V; Tamb=-40~+85℃ 8
High-level output voltage VOH 5.9 V VI=VIH or VIL; IO=-20uA; VCC=6.0V; Tamb=-40~+85℃ 8
High-level output voltage VOH 3.84 V VI=VIH or VIL; IO=-6.0mA; VCC=4.5V; Tamb=-40~+85℃ 8
High-level output voltage VOH 5.34 V VI=VIH or VIL; IO=-7.8mA; VCC=6.0V; Tamb=-40~+85℃ 8
Low-level output voltage VOL 0.1 V VI=VIH or VIL; IO=20uA; VCC=2.0V; Tamb=-40~+85℃ 8
Low-level output voltage VOL 0.33 V VI=VIH or VIL; IO=6.0mA; VCC=4.5V; Tamb=-40~+85℃ 8
Input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V; Tamb=-40~+85℃ 8
Off-state output current IOZ -5 5 uA VI=VIH or VI; VCC=6.0V; VO=VCC or GND; Tamb=-40~+85℃ 9
Quiescent supply current ICC 80 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=-40~+85℃ 9
Input leakage current II -0.1 0.1 uA VI=VCC or GND; VCC=6.0V; Tamb=25℃ 7
Quiescent supply current ICC 8 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=25℃ 7
CP to Qn propagation delay tpd 190 ns VCC=2.0V; CL=50pF; Tamb=-40~+85℃ 11
CP to Qn propagation delay tpd 35 ns VCC=4.5V; CL=50pF; Tamb=-40~+85℃ 11
CP to Qn propagation delay tpd 33 ns VCC=6.0V; CL=50pF; Tamb=-40~+85℃ 11
OE to Qn enable time ten 175 ns VCC=2.0V; CL=50pF; Tamb=-40~+85℃ 11
OE to Qn enable time ten 35 ns VCC=4.5V; CL=50pF; Tamb=-40~+85℃ 11
OE to Qn enable time ten 30 ns VCC=6.0V; CL=50pF; Tamb=-40~+85℃ 11
OE to Qn disable time tdis 155 ns VCC=2.0V; CL=50pF; Tamb=-40~+85℃ 11
OE to Qn disable time tdis 31 ns VCC=4.5V; CL=50pF; Tamb=-40~+85℃ 11
OE to Qn disable time tdis 26 ns VCC=6.0V; CL=50pF; Tamb=-40~+85℃ 11
Transition time tt 75 ns Qn output; VCC=2.0V; CL=50pF; Tamb=-40~+85℃ 11
Transition time tt 15 ns Qn output; VCC=4.5V; CL=50pF; Tamb=-40~+85℃ 11
Transition time tt 13 ns Qn output; VCC=6.0V; CL=50pF; Tamb=-40~+85℃ 11
Pulse width tW 100 ns CP high or low; VCC=2.0V; Tamb=-40~+85℃ 11
Pulse width tW 20 ns CP high or low; VCC=4.5V; Tamb=-40~+85℃ 11
Pulse width tW 17 ns CP high or low; VCC=6.0V; Tamb=-40~+85℃ 11
Setup time Dn to CP tsu 75 ns VCC=2.0V; Tamb=-40~+85℃ 11
Setup time Dn to CP tsu 15 ns VCC=4.5V; Tamb=-40~+85℃ 11
Setup time Dn to CP tsu 13 ns VCC=6.0V; Tamb=-40~+85℃ 11
Hold time Dn to CP th 5 ns VCC=2.0V; Tamb=-40~+85℃ 11
Maximum frequency fmax 4.8 MHz CP input; VCC=2.0V; Tamb=-40~+85℃ 11
Maximum frequency fmax 24 MHz CP input; VCC=4.5V; Tamb=-40~+85℃ 11
Maximum frequency fmax 28 MHz CP input; VCC=6.0V; Tamb=-40~+85℃ 11
Input capacitance CI 3.5 pF Tamb=25℃ 8
Power dissipation capacitance CPD 22 pF CL=50pF; f=1MHz; VI=GND~VCC 10

CAD (KiCad official)

  • Symbol: AIP74HC574TA.TR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: aip74hc574ta-tr-etched.step / aip74hc574ta-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc574ta-tr.step / aip74hc574ta-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (18 pp, sha256 32276be003c06d28, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF