component
AIP74HC574SA20.TR
Public Made by Adomby adom
Wuxi I core Elec Flip Flops, SOP20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AIP74HC574SA20.TR
Wuxi I core Elec · Flip Flops · SOP20
AIP74HC574SA20.TR from Wuxi I core Elec, in a SOP20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-LOW 3-state output enable input; a HIGH causes outputs Q0 to Q7 to assume the high-impedance OFF-state without changing the flip-flop contents. |
| 2 | D0 | input | Data input for flip-flop 0, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 3 | D1 | input | Data input for flip-flop 1, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 4 | D2 | input | Data input for flip-flop 2, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 5 | D3 | input | Data input for flip-flop 3, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 6 | D4 | input | Data input for flip-flop 4, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 7 | D5 | input | Data input for flip-flop 5, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 8 | D6 | input | Data input for flip-flop 6, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 9 | D7 | input | Data input for flip-flop 7, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages. |
| 11 | CP | input | Clock input; the flip-flops store the state of their Dn inputs on the LOW-to-HIGH clock transition. |
| 12 | Q7 | tri_state | 3-state non-inverting flip-flop output 7, high-impedance when OE is HIGH. |
| 13 | Q6 | tri_state | 3-state non-inverting flip-flop output 6, high-impedance when OE is HIGH. |
| 14 | Q5 | tri_state | 3-state non-inverting flip-flop output 5, high-impedance when OE is HIGH. |
| 15 | Q4 | tri_state | 3-state non-inverting flip-flop output 4, high-impedance when OE is HIGH. |
| 16 | Q3 | tri_state | 3-state non-inverting flip-flop output 3, high-impedance when OE is HIGH. |
| 17 | Q2 | tri_state | 3-state non-inverting flip-flop output 2, high-impedance when OE is HIGH. |
| 18 | Q1 | tri_state | 3-state non-inverting flip-flop output 1, high-impedance when OE is HIGH. |
| 19 | Q0 | tri_state | 3-state non-inverting flip-flop output 0, high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for AiP74HC574 (4.5 V to 5.5 V for AiP74HCT574 variant). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 7 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 7 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 7 | |
| output current | IO | -35 | 35 | mA | -0.5V < VO < VCC+0.5V | 7 | |
| supply current | ICC | 70 | mA | 7 | |||
| ground current | IGND | -70 | mA | 7 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| total power dissipation | Ptot | 500 | mW | 7 | |||
| supply voltage (AiP74HC574) | VCC | 2 | 5 | 6 | V | 8 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 8 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 8 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 8 | ||
| ambient temperature | Tamb | -40 | 105 | ℃ | 8 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC=2.0V (Tamb=25℃) | 8 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC=4.5V (Tamb=25℃) | 8 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC=6.0V (Tamb=25℃) | 8 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC=2.0V (Tamb=25℃) | 8 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC=4.5V (Tamb=25℃) | 8 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC=6.0V (Tamb=25℃) | 8 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | IO=-20uA; VCC=2.0V (Tamb=25℃) | 8 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | IO=-20uA; VCC=4.5V (Tamb=25℃) | 8 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | IO=-20uA; VCC=6.0V (Tamb=25℃) | 8 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | IO=-6.0mA; VCC=4.5V (Tamb=25℃) | 8 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | IO=-7.8mA; VCC=6.0V (Tamb=25℃) | 8 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | IO=20uA; VCC=2.0V (Tamb=25℃) | 8 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | IO=6.0mA; VCC=4.5V (Tamb=25℃) | 8 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | IO=7.8mA; VCC=6.0V (Tamb=25℃) | 8 | |
| input leakage current | II | -0.1 | 0.1 | uA | VI=VCC or GND; VCC=6.0V (Tamb=25℃) | 8 | |
| OFF-state output current | IOZ | -0.5 | 0.5 | uA | VI=VIH or VIL; VCC=6.0V; VO=VCC or GND (Tamb=25℃) | 8 | |
| supply current | ICC | 8 | uA | VI=VCC or GND; IO=0A; VCC=6.0V (Tamb=25℃) | 8 | ||
| CP to Qn propagation delay | tpd | 47 | 150 | ns | VCC=2.0V; see Figure 6 (Tamb=25℃) | 11 | |
| CP to Qn propagation delay | tpd | 17 | 30 | ns | VCC=4.5V; see Figure 6 (Tamb=25℃) | 11 | |
| CP to Qn propagation delay | tpd | 14 | 26 | ns | VCC=6.0V; see Figure 6 (Tamb=25℃) | 11 | |
| OE to Qn enable time | ten | 44 | 140 | ns | VCC=2.0V; see Figure 8 (Tamb=25℃) | 11 | |
| OE to Qn enable time | ten | 16 | 28 | ns | VCC=4.5V; see Figure 8 (Tamb=25℃) | 11 | |
| OE to Qn enable time | ten | 13 | 24 | ns | VCC=6.0V; see Figure 8 (Tamb=25℃) | 11 | |
| OE to Qn disable time | tdis | 39 | 125 | ns | VCC=2.0V; see Figure 8 (Tamb=25℃) | 11 | |
| OE to Qn disable time | tdis | 14 | 25 | ns | VCC=4.5V; see Figure 8 (Tamb=25℃) | 11 | |
| OE to Qn disable time | tdis | 11 | 21 | ns | VCC=6.0V; see Figure 8 (Tamb=25℃) | 11 | |
| transition time | tt | 14 | 60 | ns | Qn output; VCC=2.0V; see Figure 6 (Tamb=25℃) | 11 | |
| transition time | tt | 5 | 12 | ns | Qn output; VCC=4.5V; see Figure 6 (Tamb=25℃) | 11 | |
| transition time | tt | 4 | 10 | ns | Qn output; VCC=6.0V; see Figure 6 (Tamb=25℃) | 11 | |
| pulse width CP HIGH or LOW | tW | 80 | 14 | ns | VCC=2.0V; see Figure 7 (Tamb=25℃) | 11 | |
| pulse width CP HIGH or LOW | tW | 16 | 5 | ns | VCC=4.5V; see Figure 7 (Tamb=25℃) | 11 | |
| pulse width CP HIGH or LOW | tW | 14 | 4 | ns | VCC=6.0V; see Figure 7 (Tamb=25℃) | 11 | |
| Dn to CP set-up time | tsu | 60 | 6 | ns | VCC=2.0V; see Figure 7 (Tamb=25℃) | 11 | |
| Dn to CP set-up time | tsu | 12 | 2 | ns | VCC=4.5V; see Figure 7 (Tamb=25℃) | 11 | |
| Dn to CP set-up time | tsu | 10 | 2 | ns | VCC=6.0V; see Figure 7 (Tamb=25℃) | 11 | |
| Dn to CP hold time | th | 5 | 0 | ns | VCC=2.0V; see Figure 7 (Tamb=25℃) | 11 | |
| maximum frequency | fmax | 6 | 37 | MHz | CP input; VCC=2.0V; see Figure 6 (Tamb=25℃) | 11 | |
| maximum frequency | fmax | 30 | 112 | MHz | CP input; VCC=4.5V; see Figure 6 (Tamb=25℃) | 12 | |
| maximum frequency | fmax | 35 | 133 | MHz | CP input; VCC=6.0V; see Figure 6 (Tamb=25℃) | 12 | |
| supply current | ICC | 80 | uA | VI=VCC or GND; IO=0A; VCC=6.0V (Tamb=-40℃ to +85℃) | 10 | ||
| supply current | ICC | 160 | uA | VI=VCC or GND; IO=0A; VCC=6.0V (Tamb=-40℃ to +105℃) | 10 | ||
| input leakage current | II | -1 | 1 | uA | VI=VCC or GND; VCC=6.0V (Tamb=-40℃ to +105℃) | 10 | |
| CP to Qn propagation delay | tpd | 45 | ns | VCC=4.5V; see Figure 6 (Tamb=-40℃ to +105℃) | 14 |
CAD (KiCad official)
- Symbol:
AIP74HC574SA20.TR - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
aip74hc574sa20-tr-etched.step/aip74hc574sa20-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc574sa20-tr.step/aip74hc574sa20-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (20 pp, sha256
4456dfec12c37aa8, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AIP74HC574SA20.TR
**Wuxi I core Elec** · Flip Flops · SOP20
AIP74HC574SA20.TR from Wuxi I core Elec, in a SOP20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-LOW 3-state output enable input; a HIGH causes outputs Q0 to Q7 to assume the high-impedance OFF-state without changing the flip-flop contents. |
| 2 | D0 | input | Data input for flip-flop 0, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 3 | D1 | input | Data input for flip-flop 1, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 4 | D2 | input | Data input for flip-flop 2, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 5 | D3 | input | Data input for flip-flop 3, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 6 | D4 | input | Data input for flip-flop 4, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 7 | D5 | input | Data input for flip-flop 5, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 8 | D6 | input | Data input for flip-flop 6, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 9 | D7 | input | Data input for flip-flop 7, sampled on the LOW-to-HIGH transition of CP and required to meet the set-up and hold times. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages. |
| 11 | CP | input | Clock input; the flip-flops store the state of their Dn inputs on the LOW-to-HIGH clock transition. |
| 12 | Q7 | tri_state | 3-state non-inverting flip-flop output 7, high-impedance when OE is HIGH. |
| 13 | Q6 | tri_state | 3-state non-inverting flip-flop output 6, high-impedance when OE is HIGH. |
| 14 | Q5 | tri_state | 3-state non-inverting flip-flop output 5, high-impedance when OE is HIGH. |
| 15 | Q4 | tri_state | 3-state non-inverting flip-flop output 4, high-impedance when OE is HIGH. |
| 16 | Q3 | tri_state | 3-state non-inverting flip-flop output 3, high-impedance when OE is HIGH. |
| 17 | Q2 | tri_state | 3-state non-inverting flip-flop output 2, high-impedance when OE is HIGH. |
| 18 | Q1 | tri_state | 3-state non-inverting flip-flop output 1, high-impedance when OE is HIGH. |
| 19 | Q0 | tri_state | 3-state non-inverting flip-flop output 0, high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for AiP74HC574 (4.5 V to 5.5 V for AiP74HCT574 variant). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP20 |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 7 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 7 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 7 |
| output current | IO | -35 | | 35 | mA | -0.5V < VO < VCC+0.5V | 7 |
| supply current | ICC | | | 70 | mA | | 7 |
| ground current | IGND | -70 | | | mA | | 7 |
| storage temperature | Tstg | -65 | | 150 | ℃ | | 7 |
| total power dissipation | Ptot | | | 500 | mW | | 7 |
| supply voltage (AiP74HC574) | VCC | 2 | 5 | 6 | V | | 8 |
| input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 8 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 8 |
| input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 8 |
| ambient temperature | Tamb | -40 | | 105 | ℃ | | 8 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 | | V | VCC=2.0V (Tamb=25℃) | 8 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | | V | VCC=4.5V (Tamb=25℃) | 8 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | | V | VCC=6.0V (Tamb=25℃) | 8 |
| LOW-level input voltage | VIL | | 0.8 | 0.5 | V | VCC=2.0V (Tamb=25℃) | 8 |
| LOW-level input voltage | VIL | | 2.1 | 1.35 | V | VCC=4.5V (Tamb=25℃) | 8 |
| LOW-level input voltage | VIL | | 2.8 | 1.8 | V | VCC=6.0V (Tamb=25℃) | 8 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | IO=-20uA; VCC=2.0V (Tamb=25℃) | 8 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | IO=-20uA; VCC=4.5V (Tamb=25℃) | 8 |
| HIGH-level output voltage | VOH | 5.9 | 6 | | V | IO=-20uA; VCC=6.0V (Tamb=25℃) | 8 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | | V | IO=-6.0mA; VCC=4.5V (Tamb=25℃) | 8 |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | | V | IO=-7.8mA; VCC=6.0V (Tamb=25℃) | 8 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | IO=20uA; VCC=2.0V (Tamb=25℃) | 8 |
| LOW-level output voltage | VOL | | 0.15 | 0.26 | V | IO=6.0mA; VCC=4.5V (Tamb=25℃) | 8 |
| LOW-level output voltage | VOL | | 0.16 | 0.26 | V | IO=7.8mA; VCC=6.0V (Tamb=25℃) | 8 |
| input leakage current | II | -0.1 | | 0.1 | uA | VI=VCC or GND; VCC=6.0V (Tamb=25℃) | 8 |
| OFF-state output current | IOZ | -0.5 | | 0.5 | uA | VI=VIH or VIL; VCC=6.0V; VO=VCC or GND (Tamb=25℃) | 8 |
| supply current | ICC | | | 8 | uA | VI=VCC or GND; IO=0A; VCC=6.0V (Tamb=25℃) | 8 |
| CP to Qn propagation delay | tpd | | 47 | 150 | ns | VCC=2.0V; see Figure 6 (Tamb=25℃) | 11 |
| CP to Qn propagation delay | tpd | | 17 | 30 | ns | VCC=4.5V; see Figure 6 (Tamb=25℃) | 11 |
| CP to Qn propagation delay | tpd | | 14 | 26 | ns | VCC=6.0V; see Figure 6 (Tamb=25℃) | 11 |
| OE to Qn enable time | ten | | 44 | 140 | ns | VCC=2.0V; see Figure 8 (Tamb=25℃) | 11 |
| OE to Qn enable time | ten | | 16 | 28 | ns | VCC=4.5V; see Figure 8 (Tamb=25℃) | 11 |
| OE to Qn enable time | ten | | 13 | 24 | ns | VCC=6.0V; see Figure 8 (Tamb=25℃) | 11 |
| OE to Qn disable time | tdis | | 39 | 125 | ns | VCC=2.0V; see Figure 8 (Tamb=25℃) | 11 |
| OE to Qn disable time | tdis | | 14 | 25 | ns | VCC=4.5V; see Figure 8 (Tamb=25℃) | 11 |
| OE to Qn disable time | tdis | | 11 | 21 | ns | VCC=6.0V; see Figure 8 (Tamb=25℃) | 11 |
| transition time | tt | | 14 | 60 | ns | Qn output; VCC=2.0V; see Figure 6 (Tamb=25℃) | 11 |
| transition time | tt | | 5 | 12 | ns | Qn output; VCC=4.5V; see Figure 6 (Tamb=25℃) | 11 |
| transition time | tt | | 4 | 10 | ns | Qn output; VCC=6.0V; see Figure 6 (Tamb=25℃) | 11 |
| pulse width CP HIGH or LOW | tW | 80 | 14 | | ns | VCC=2.0V; see Figure 7 (Tamb=25℃) | 11 |
| pulse width CP HIGH or LOW | tW | 16 | 5 | | ns | VCC=4.5V; see Figure 7 (Tamb=25℃) | 11 |
| pulse width CP HIGH or LOW | tW | 14 | 4 | | ns | VCC=6.0V; see Figure 7 (Tamb=25℃) | 11 |
| Dn to CP set-up time | tsu | 60 | 6 | | ns | VCC=2.0V; see Figure 7 (Tamb=25℃) | 11 |
| Dn to CP set-up time | tsu | 12 | 2 | | ns | VCC=4.5V; see Figure 7 (Tamb=25℃) | 11 |
| Dn to CP set-up time | tsu | 10 | 2 | | ns | VCC=6.0V; see Figure 7 (Tamb=25℃) | 11 |
| Dn to CP hold time | th | 5 | 0 | | ns | VCC=2.0V; see Figure 7 (Tamb=25℃) | 11 |
| maximum frequency | fmax | 6 | 37 | | MHz | CP input; VCC=2.0V; see Figure 6 (Tamb=25℃) | 11 |
| maximum frequency | fmax | 30 | 112 | | MHz | CP input; VCC=4.5V; see Figure 6 (Tamb=25℃) | 12 |
| maximum frequency | fmax | 35 | 133 | | MHz | CP input; VCC=6.0V; see Figure 6 (Tamb=25℃) | 12 |
| supply current | ICC | | | 80 | uA | VI=VCC or GND; IO=0A; VCC=6.0V (Tamb=-40℃ to +85℃) | 10 |
| supply current | ICC | | | 160 | uA | VI=VCC or GND; IO=0A; VCC=6.0V (Tamb=-40℃ to +105℃) | 10 |
| input leakage current | II | -1 | | 1 | uA | VI=VCC or GND; VCC=6.0V (Tamb=-40℃ to +105℃) | 10 |
| CP to Qn propagation delay | tpd | | | 45 | ns | VCC=4.5V; see Figure 6 (Tamb=-40℃ to +105℃) | 14 |
## CAD (KiCad official)
- Symbol: `AIP74HC574SA20.TR`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `aip74hc574sa20-tr-etched.step` / `aip74hc574sa20-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aip74hc574sa20-tr.step` / `aip74hc574sa20-tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Wuxi I core Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603012002352943104) (20 pp, sha256 `4456dfec12c37aa8`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/aip74hc574sa20-tr-datasheet.pdf)