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Contents

README

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AiP74HC541TA20.TR

Wuxi I-core Elec · Buffers, Drivers, Receivers, Transceivers · TSSOP-20

AiP74HC541TA20.TR from Wuxi I-core Elec, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Output enable input, active low; a high level on OE1 forces outputs Y0-Y3 into the high-impedance state.
2 A0 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
3 A1 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
4 A2 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
5 A3 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
6 A4 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
7 A5 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
8 A6 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
9 A7 input Data input; CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541, with internal clamp diodes allowing voltages above VCC through a current-limiting resistor.
10 GND power_in Ground (0 V) reference for the device.
11 Y7 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
12 Y6 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
13 Y5 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
14 Y4 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
15 Y3 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
16 Y2 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
17 Y1 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
18 Y0 tri_state Non-inverting three-state data output; high impedance when OE1 or OE2 is high.
19 OE2 input Output enable input, active low; a high level on OE2 forces outputs Y4-Y7 into the high-impedance state.
20 VCC power_in Supply voltage: 2.0 V to 6.0 V recommended for AiP74HC541 and 4.5 V to 5.5 V for AiP74HCT541, absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 7
Input clamp current IIK -20 20 mA VI<-0.5V 或 VI>VCC+0.5V 7
Output clamp current IOK -20 20 mA VO<-0.5V 或 VO>VCC+0.5V 7
Output current IO -35 35 mA -0.5V<VO<VCC+0.5V 7
Supply current ICC 70 mA 7
Ground current IGND -70 mA 7
Storage temperature Tstg -65 150 ℃ 7
Total power dissipation Ptot 500 mW 7
Supply voltage VCC 2 5 6 V 7
Input voltage VI 0 V 7
Output voltage VO 0 V 7
Input rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 7
Input rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 7
Input rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 7
Operating ambient temperature Tamb -40 105 ℃ 7
High-level input voltage VIH 1.5 V Tamb=-40℃~+105℃; VCC=2.0V 10
High-level input voltage VIH 3.15 V Tamb=-40℃~+105℃; VCC=4.5V 10
High-level input voltage VIH 4.2 V Tamb=-40℃~+105℃; VCC=6.0V 10
Low-level input voltage VIL 0.5 V Tamb=-40℃~+105℃; VCC=2.0V 10
Low-level input voltage VIL 1.35 V Tamb=-40℃~+105℃; VCC=4.5V 10
Low-level input voltage VIL 1.8 V Tamb=-40℃~+105℃; VCC=6.0V 10
High-level output voltage VOH 1.9 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=-20uA; VCC=2.0V 10
High-level output voltage VOH 4.4 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=-20uA; VCC=4.5V 10
High-level output voltage VOH 5.9 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=-20uA; VCC=6.0V 10
High-level output voltage VOH 3.7 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=-6.0mA; VCC=4.5V 10
High-level output voltage VOH 5.2 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=-7.8mA; VCC=6.0V 10
Low-level output voltage VOL 0.1 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=20uA; VCC=2.0V 10
Low-level output voltage VOL 0.4 V Tamb=-40℃~+105℃; VI=VIH或VIL; IO=6.0mA; VCC=4.5V 10
Input leakage current II -1 1 uA Tamb=-40℃~+105℃; VI=VCC或GND; VCC=6.0V 10
Off-state output current IOZ -10 10 uA Tamb=-40℃~+105℃; VI=VIH或VIL; VCC=6.0V; VO=VCC或GND 10
Quiescent supply current ICC 160 uA Tamb=-40℃~+105℃; VI=VCC或GND; IO=0A; VCC=6.0V 10
Propagation delay An to Yn tpd 175 ns Tamb=-40℃~+105℃; CL=50pF; VCC=2.0V; 见图6 13
Propagation delay An to Yn tpd 35 ns Tamb=-40℃~+105℃; CL=50pF; VCC=4.5V; 见图6 13
Propagation delay An to Yn tpd 30 ns Tamb=-40℃~+105℃; CL=50pF; VCC=6.0V; 见图6 13
Enable time OEn to Yn ten 240 ns Tamb=-40℃~+105℃; CL=50pF; VCC=2.0V; 见图7 13
Enable time OEn to Yn ten 48 ns Tamb=-40℃~+105℃; CL=50pF; VCC=4.5V; 见图7 13
Enable time OEn to Yn ten 41 ns Tamb=-40℃~+105℃; CL=50pF; VCC=6.0V; 见图7 13
Disable time OEn to Yn tdis 240 ns Tamb=-40℃~+105℃; CL=50pF; VCC=2.0V; 见图7 13
Disable time OEn to Yn tdis 48 ns Tamb=-40℃~+105℃; CL=50pF; VCC=4.5V; 见图7 13
Disable time OEn to Yn tdis 41 ns Tamb=-40℃~+105℃; CL=50pF; VCC=6.0V; 见图7 13
Transition time tt 90 ns Tamb=-40℃~+105℃; CL=50pF; VCC=2.0V; 见图6 13
Transition time tt 18 ns Tamb=-40℃~+105℃; CL=50pF; VCC=4.5V; 见图6 13
Transition time tt 15 ns Tamb=-40℃~+105℃; CL=50pF; VCC=6.0V; 见图6 13
Propagation delay An to Yn tpd 33 115 ns Tamb=25℃; CL=50pF; VCC=2.0V; 见图6 11
Propagation delay An to Yn tpd 12 23 ns Tamb=25℃; CL=50pF; VCC=4.5V; 见图6 11
Propagation delay An to Yn tpd 10 20 ns Tamb=25℃; CL=50pF; VCC=6.0V; 见图6 11
Enable time OEn to Yn ten 55 160 ns Tamb=25℃; CL=50pF; VCC=2.0V; 见图7 11
Enable time OEn to Yn ten 20 32 ns Tamb=25℃; CL=50pF; VCC=4.5V; 见图7 11
Enable time OEn to Yn ten 16 27 ns Tamb=25℃; CL=50pF; VCC=6.0V; 见图7 11
Disable time OEn to Yn tdis 61 160 ns Tamb=25℃; CL=50pF; VCC=2.0V; 见图7 11
Disable time OEn to Yn tdis 22 32 ns Tamb=25℃; CL=50pF; VCC=4.5V; 见图7 11
Disable time OEn to Yn tdis 18 27 ns Tamb=25℃; CL=50pF; VCC=6.0V; 见图7 11
Transition time tt 14 60 ns Tamb=25℃; CL=50pF; VCC=2.0V; 见图6 11
Transition time tt 5 12 ns Tamb=25℃; CL=50pF; VCC=4.5V; 见图6 11
Transition time tt 4 10 ns Tamb=25℃; CL=50pF; VCC=6.0V; 见图6 11
Propagation delay An to Yn tpd 10 ns Tamb=25℃; VCC=5.0V; CL=15pF 11
Power dissipation capacitance CPD 37 pF 每个缓冲器; VI=GND~VCC 11

CAD (KiCad official)

  • Symbol: AiP74HC541TA20.TR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: aip74hc541ta20-tr-etched.step / aip74hc541ta20-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc541ta20-tr.step / aip74hc541ta20-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (19 pp, sha256 0c450dccd30c7d2c, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF