component
AIP74HC541SA20.TR
Public Made by Adomby adom
Wuxi I core Elec Buffers, Drivers, Receivers, Transceivers, SOP-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
AIP74HC541SA20.TR
Wuxi I core Elec · Buffers, Drivers, Receivers, Transceivers · SOP-20-300mil
AIP74HC541SA20.TR from Wuxi I core Elec, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-LOW output enable input; a HIGH level on OE1 forces the Y outputs into the high-impedance OFF-state. |
| 2 | A0 | input | Data input for channel 0; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 3 | A1 | input | Data input for channel 1; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 4 | A2 | input | Data input for channel 2; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 5 | A3 | input | Data input for channel 3; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 6 | A4 | input | Data input for channel 4; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 7 | A5 | input | Data input for channel 5; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 8 | A6 | input | Data input for channel 6; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 9 | A7 | input | Data input for channel 7; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 10 | GND | power_in | Ground (0 V) reference for all device voltages. |
| 11 | Y7 | tri_state | Non-inverting 3-state data output for channel 7 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 12 | Y6 | tri_state | Non-inverting 3-state data output for channel 6 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 13 | Y5 | tri_state | Non-inverting 3-state data output for channel 5 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 14 | Y4 | tri_state | Non-inverting 3-state data output for channel 4 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 15 | Y3 | tri_state | Non-inverting 3-state data output for channel 3 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 16 | Y2 | tri_state | Non-inverting 3-state data output for channel 2 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 17 | Y1 | tri_state | Non-inverting 3-state data output for channel 1 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 18 | Y0 | tri_state | Non-inverting 3-state data output for channel 0 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 19 | OE2 | input | Active-LOW output enable input; a HIGH level on OE2 forces the Y outputs into the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage: recommended 2.0 V to 6.0 V for AiP74HC541 and 4.5 V to 5.5 V for AiP74HCT541, with absolute maximum 7.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 8 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 8 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 8 | |
| output current | IO | -35 | 35 | mA | -0.5V < VO < VCC+0.5V | 8 | |
| supply current | ICC | 70 | mA | 8 | |||
| ground current | IGND | -70 | mA | 8 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| total power dissipation | Ptot | 500 | mW | 8 | |||
| soldering temperature | TL | 250 | ℃ | 10s, SOP20 | 8 | ||
| supply voltage (AiP74HC541) | VCC | 2 | 5 | 6 | V | 8 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 8 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 8 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 8 | ||
| ambient temperature | Tamb | -40 | 105 | ℃ | 8 | ||
| HIGH-level input voltage | VIH | 1.5 | V | Tamb=-40℃ to +105℃; VCC=2.0V | 11 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=-40℃ to +105℃; VCC=4.5V | 11 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=-40℃ to +105℃; VCC=6.0V | 11 | ||
| LOW-level input voltage | VIL | 0.5 | V | Tamb=-40℃ to +105℃; VCC=2.0V | 11 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=-40℃ to +105℃; VCC=4.5V | 11 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=-40℃ to +105℃; VCC=6.0V | 11 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=2.0V | 11 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=4.5V | 11 | ||
| HIGH-level output voltage | VOH | 5.9 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=6.0V | 11 | ||
| HIGH-level output voltage | VOH | 3.7 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 11 | ||
| HIGH-level output voltage | VOH | 5.2 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-7.8mA; VCC=6.0V | 11 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=20uA; VCC=2.0V | 11 | ||
| LOW-level output voltage | VOL | 0.4 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 11 | ||
| input leakage current | II | -1 | 1 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; VCC=6.0V | 11 | |
| OFF-state output current | IOZ | -10 | 10 | uA | Tamb=-40℃ to +105℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 11 | |
| supply current | ICC | 160 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; IO=0A; VCC=6.0V | 11 | ||
| An to Yn propagation delay | tpd | 175 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 6 | 14 | ||
| An to Yn propagation delay | tpd | 35 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 6 | 14 | ||
| An to Yn propagation delay | tpd | 30 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 6 | 14 | ||
| OE-n to Yn enable time | ten | 240 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 7 | 14 | ||
| OE-n to Yn enable time | ten | 48 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 7 | 14 | ||
| OE-n to Yn enable time | ten | 41 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 7 | 14 | ||
| OE-n to Yn disable time | tdis | 240 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 7 | 14 | ||
| OE-n to Yn disable time | tdis | 48 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 7 | 14 | ||
| OE-n to Yn disable time | tdis | 41 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 7 | 14 | ||
| transition time | tt | 90 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 6 | 14 | ||
| transition time | tt | 18 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 6 | 14 | ||
| transition time | tt | 15 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 6 | 14 | ||
| An to Yn propagation delay | tpd | 33 | 115 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 6 | 12 | |
| An to Yn propagation delay | tpd | 12 | 23 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 6 | 12 | |
| An to Yn propagation delay | tpd | 10 | 20 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 6 | 12 | |
| OE-n to Yn enable time | ten | 55 | 160 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 7 | 12 | |
| OE-n to Yn enable time | ten | 20 | 32 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 7 | 12 | |
| OE-n to Yn enable time | ten | 16 | 27 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 7 | 12 | |
| OE-n to Yn disable time | tdis | 61 | 160 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 7 | 12 | |
| OE-n to Yn disable time | tdis | 22 | 32 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 7 | 12 | |
| OE-n to Yn disable time | tdis | 18 | 27 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 7 | 12 | |
| transition time | tt | 14 | 60 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 6 | 12 | |
| transition time | tt | 5 | 12 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 6 | 12 | |
| transition time | tt | 4 | 10 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 6 | 12 | |
| supply current | ICC | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 9 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | Tamb=25℃; VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 9 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | Tamb=25℃; VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 9 |
CAD (KiCad official)
- Symbol:
AIP74HC541SA20.TR - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
aip74hc541sa20-tr-etched.step/aip74hc541sa20-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc541sa20-tr.step/aip74hc541sa20-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (20 pp, sha256
6569b10c7e169d6a, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AIP74HC541SA20.TR
**Wuxi I core Elec** · Buffers, Drivers, Receivers, Transceivers · SOP-20-300mil
AIP74HC541SA20.TR from Wuxi I core Elec, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Active-LOW output enable input; a HIGH level on OE1 forces the Y outputs into the high-impedance OFF-state. |
| 2 | A0 | input | Data input for channel 0; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 3 | A1 | input | Data input for channel 1; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 4 | A2 | input | Data input for channel 2; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 5 | A3 | input | Data input for channel 3; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 6 | A4 | input | Data input for channel 4; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 7 | A5 | input | Data input for channel 5; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 8 | A6 | input | Data input for channel 6; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 9 | A7 | input | Data input for channel 7; the inputs have clamp diodes so current-limiting resistors can interface them to voltages above VCC, with CMOS levels for AiP74HC541 and TTL levels for AiP74HCT541. |
| 10 | GND | power_in | Ground (0 V) reference for all device voltages. |
| 11 | Y7 | tri_state | Non-inverting 3-state data output for channel 7 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 12 | Y6 | tri_state | Non-inverting 3-state data output for channel 6 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 13 | Y5 | tri_state | Non-inverting 3-state data output for channel 5 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 14 | Y4 | tri_state | Non-inverting 3-state data output for channel 4 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 15 | Y3 | tri_state | Non-inverting 3-state data output for channel 3 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 16 | Y2 | tri_state | Non-inverting 3-state data output for channel 2 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 17 | Y1 | tri_state | Non-inverting 3-state data output for channel 1 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 18 | Y0 | tri_state | Non-inverting 3-state data output for channel 0 that goes high-impedance when the output enables are inactive; absolute maximum output current is ±35 mA. |
| 19 | OE2 | input | Active-LOW output enable input; a HIGH level on OE2 forces the Y outputs into the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage: recommended 2.0 V to 6.0 V for AiP74HC541 and 4.5 V to 5.5 V for AiP74HCT541, with absolute maximum 7.0 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP-20-300mil |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 8 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 8 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 8 |
| output current | IO | -35 | | 35 | mA | -0.5V < VO < VCC+0.5V | 8 |
| supply current | ICC | | | 70 | mA | | 8 |
| ground current | IGND | -70 | | | mA | | 8 |
| storage temperature | Tstg | -65 | | 150 | ℃ | | 8 |
| total power dissipation | Ptot | | | 500 | mW | | 8 |
| soldering temperature | TL | | | 250 | ℃ | 10s, SOP20 | 8 |
| supply voltage (AiP74HC541) | VCC | 2 | 5 | 6 | V | | 8 |
| input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 8 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 8 |
| input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 8 |
| ambient temperature | Tamb | -40 | | 105 | ℃ | | 8 |
| HIGH-level input voltage | VIH | 1.5 | | | V | Tamb=-40℃ to +105℃; VCC=2.0V | 11 |
| HIGH-level input voltage | VIH | 3.15 | | | V | Tamb=-40℃ to +105℃; VCC=4.5V | 11 |
| HIGH-level input voltage | VIH | 4.2 | | | V | Tamb=-40℃ to +105℃; VCC=6.0V | 11 |
| LOW-level input voltage | VIL | | | 0.5 | V | Tamb=-40℃ to +105℃; VCC=2.0V | 11 |
| LOW-level input voltage | VIL | | | 1.35 | V | Tamb=-40℃ to +105℃; VCC=4.5V | 11 |
| LOW-level input voltage | VIL | | | 1.8 | V | Tamb=-40℃ to +105℃; VCC=6.0V | 11 |
| HIGH-level output voltage | VOH | 1.9 | | | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=2.0V | 11 |
| HIGH-level output voltage | VOH | 4.4 | | | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=4.5V | 11 |
| HIGH-level output voltage | VOH | 5.9 | | | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=6.0V | 11 |
| HIGH-level output voltage | VOH | 3.7 | | | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 11 |
| HIGH-level output voltage | VOH | 5.2 | | | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-7.8mA; VCC=6.0V | 11 |
| LOW-level output voltage | VOL | | | 0.1 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=20uA; VCC=2.0V | 11 |
| LOW-level output voltage | VOL | | | 0.4 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 11 |
| input leakage current | II | -1 | | 1 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; VCC=6.0V | 11 |
| OFF-state output current | IOZ | -10 | | 10 | uA | Tamb=-40℃ to +105℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 11 |
| supply current | ICC | | | 160 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; IO=0A; VCC=6.0V | 11 |
| An to Yn propagation delay | tpd | | | 175 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 6 | 14 |
| An to Yn propagation delay | tpd | | | 35 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 6 | 14 |
| An to Yn propagation delay | tpd | | | 30 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 6 | 14 |
| OE-n to Yn enable time | ten | | | 240 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 7 | 14 |
| OE-n to Yn enable time | ten | | | 48 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 7 | 14 |
| OE-n to Yn enable time | ten | | | 41 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 7 | 14 |
| OE-n to Yn disable time | tdis | | | 240 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 7 | 14 |
| OE-n to Yn disable time | tdis | | | 48 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 7 | 14 |
| OE-n to Yn disable time | tdis | | | 41 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 7 | 14 |
| transition time | tt | | | 90 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=2.0V; see Figure 6 | 14 |
| transition time | tt | | | 18 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=4.5V; see Figure 6 | 14 |
| transition time | tt | | | 15 | ns | Tamb=-40℃ to +105℃; CL=50pF; VCC=6.0V; see Figure 6 | 14 |
| An to Yn propagation delay | tpd | | 33 | 115 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 6 | 12 |
| An to Yn propagation delay | tpd | | 12 | 23 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 6 | 12 |
| An to Yn propagation delay | tpd | | 10 | 20 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 6 | 12 |
| OE-n to Yn enable time | ten | | 55 | 160 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 7 | 12 |
| OE-n to Yn enable time | ten | | 20 | 32 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 7 | 12 |
| OE-n to Yn enable time | ten | | 16 | 27 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 7 | 12 |
| OE-n to Yn disable time | tdis | | 61 | 160 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 7 | 12 |
| OE-n to Yn disable time | tdis | | 22 | 32 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 7 | 12 |
| OE-n to Yn disable time | tdis | | 18 | 27 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 7 | 12 |
| transition time | tt | | 14 | 60 | ns | Tamb=25℃; CL=50pF; VCC=2.0V; see Figure 6 | 12 |
| transition time | tt | | 5 | 12 | ns | Tamb=25℃; CL=50pF; VCC=4.5V; see Figure 6 | 12 |
| transition time | tt | | 4 | 10 | ns | Tamb=25℃; CL=50pF; VCC=6.0V; see Figure 6 | 12 |
| supply current | ICC | | | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 9 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | | V | Tamb=25℃; VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 9 |
| LOW-level output voltage | VOL | | 0.15 | 0.26 | V | Tamb=25℃; VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 9 |
## CAD (KiCad official)
- Symbol: `AIP74HC541SA20.TR`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `aip74hc541sa20-tr-etched.step` / `aip74hc541sa20-tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aip74hc541sa20-tr.step` / `aip74hc541sa20-tr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Wuxi I core Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590234471845818368) (20 pp, sha256 `6569b10c7e169d6a`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/aip74hc541sa20-tr-datasheet.pdf)