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AiP74HC4094SA16.TB
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Wuxi I core Elec Inverters, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AiP74HC4094SA16.TB
Wuxi I core Elec · Inverters · SOP-16
AiP74HC4094SA16.TB from Wuxi I core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input: data in each shift register stage is transferred to the storage register when STR is HIGH. |
| 2 | D | input | Serial data input, shifted into the 8-stage register on positive-going clock transitions. |
| 3 | CP | input | Clock input: data is shifted on positive-going clock transitions. |
| 4 | QP0 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 5 | QP1 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 6 | QP2 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 7 | QP3 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 8 | VSS | power_in | Ground (0V) reference; the recommended VDD range of 3V to 15V is referenced to VSS. |
| 9 | QS1 | output | Serial output for cascading that carries serial data on positive-going clock edges, allowing high-speed operation with a fast clock rise time. |
| 10 | QS2 | output | Serial output for cascading that carries the same serial data as QS1 on the next negative-going clock edge, used when the clock has a slow rise time. |
| 11 | QP7 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 12 | QP6 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 13 | QP5 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 14 | QP4 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 15 | OE | input | Output enable input: the parallel outputs are active when OE is HIGH and go to high-impedance OFF-state when OE is LOW. |
| 16 | VDD | power_in | Supply voltage; recommended range is 3V to 15V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VDD | -0.5 | 18 | V | 6 | ||
| DC input current | IIK | -10 | 10 | mA | any one input | 6 | |
| input voltage | VI | -0.5 | V | all inputs; max printed as VDD+0.5 V | 6 | ||
| storage temperature | Tstg | -65 | 150 | ℃ | 6 | ||
| total power dissipation | Ptot | 500 | mW | 6 | |||
| device dissipation per output transistor | P | 100 | mW | per output transistor | 6 | ||
| supply voltage | VDD | 3 | 15 | V | 7 | ||
| ambient temperature | Tamb | -40 | 105 | ℃ | in free air | 7 | |
| data setup time | tsu | 125 | ns | VDD=5V | 7 | ||
| data setup time | tsu | 55 | ns | VDD=10V | 7 | ||
| data setup time | tsu | 35 | ns | VDD=15V | 7 | ||
| clock pulse width | tw | 200 | ns | VDD=5V | 7 | ||
| clock pulse width | tw | 100 | ns | VDD=10V | 7 | ||
| clock pulse width | tw | 83 | ns | VDD=15V | 7 | ||
| clock input frequency | fmax | 1.25 | MHz | VDD=5V; printed minimum is dc | 7 | ||
| clock input frequency | fmax | 2.5 | MHz | VDD=10V | 7 | ||
| clock input frequency | fmax | 3 | MHz | VDD=15V | 7 | ||
| supply current | IDD | 5 | uA | Tamb=-40℃; VIN=0, 5 V; VDD=5 V | 9 | ||
| supply current | IDD | 150 | uA | Tamb=+105℃; VIN=0, 5 V; VDD=5 V | 9 | ||
| supply current | IDD | 10 | uA | Tamb=-40℃; VIN=0, 10 V; VDD=10 V | 9 | ||
| supply current | IDD | 300 | uA | Tamb=+105℃; VIN=0, 10 V; VDD=10 V | 9 | ||
| supply current | IDD | 20 | uA | Tamb=-40℃; VIN=0, 15 V; VDD=15 V | 9 | ||
| supply current | IDD | 600 | uA | Tamb=+105℃; VIN=0, 15 V; VDD=15 V | 9 | ||
| LOW-level output current | IOL | 0.61 | mA | Tamb=-40℃; VO=0.4 V; VIN=0, 5 V; VDD=5 V | 9 | ||
| LOW-level output current | IOL | 0.36 | mA | Tamb=+105℃; VO=0.4 V; VIN=0, 5 V; VDD=5 V | 9 | ||
| LOW-level output current | IOL | 1.5 | mA | Tamb=-40℃; VO=0.5 V; VIN=0, 10 V; VDD=10 V | 9 | ||
| LOW-level output current | IOL | 0.9 | mA | Tamb=+105℃; VO=0.5 V; VIN=0, 10 V; VDD=10 V | 9 | ||
| LOW-level output current | IOL | 4 | mA | Tamb=-40℃; VO=1.5 V; VIN=0, 15 V; VDD=15 V | 9 | ||
| LOW-level output current | IOL | 2.4 | mA | Tamb=+105℃; VO=1.5 V; VIN=0, 15 V; VDD=15 V | 9 | ||
| HIGH-level output current | IOH | -0.61 | mA | Tamb=-40℃; VO=4.6 V; VIN=0, 5 V; VDD=5 V | 9 | ||
| HIGH-level output current | IOH | -0.36 | mA | Tamb=+105℃; VO=4.6 V; VIN=0, 5 V; VDD=5 V | 9 | ||
| HIGH-level output current | IOH | -1.8 | mA | Tamb=-40℃; VO=2.5 V; VIN=0, 5 V; VDD=5 V | 9 | ||
| HIGH-level output current | IOH | -1.15 | mA | Tamb=+105℃; VO=2.5 V; VIN=0, 5 V; VDD=5 V | 9 | ||
| HIGH-level output current | IOH | -1.5 | mA | Tamb=-40℃; VO=9.5 V; VIN=0, 10 V; VDD=10 V | 9 | ||
| HIGH-level output current | IOH | -0.9 | mA | Tamb=+105℃; VO=9.5 V; VIN=0, 10 V; VDD=10 V | 9 | ||
| HIGH-level output current | IOH | -4 | mA | Tamb=-40℃; VO=13.5 V; VIN=0, 15 V; VDD=15 V | 9 | ||
| HIGH-level output current | IOH | -2.4 | mA | Tamb=+105℃; VO=13.5 V; VIN=0, 15 V; VDD=15 V | 9 | ||
| LOW-level output voltage | VOL | 0.05 | V | Tamb=-40℃; VIN=0, 5 V; VDD=5 V | 9 | ||
| HIGH-level output voltage | VOH | 4.95 | V | Tamb=-40℃; VIN=0, 5 V; VDD=5 V | 9 | ||
| HIGH-level output voltage | VOH | 9.95 | V | Tamb=-40℃; VIN=0, 10 V; VDD=10 V | 9 | ||
| HIGH-level output voltage | VOH | 14.95 | V | Tamb=-40℃; VIN=0, 15 V; VDD=15 V | 9 | ||
| LOW-level input voltage | VIL | 1.5 | V | Tamb=-40℃; VO=0.5, 4.5 V; VDD=5 V | 9 | ||
| LOW-level input voltage | VIL | 3 | V | Tamb=-40℃; VO=1, 9 V; VDD=10 V | 9 | ||
| LOW-level input voltage | VIL | 4 | V | Tamb=-40℃; VO=1.5, 13.5 V; VDD=15 V | 9 | ||
| HIGH-level input voltage | VIH | 3.5 | V | Tamb=-40℃; VO=0.5, 4.5 V; VDD=5 V | 9 | ||
| HIGH-level input voltage | VIH | 7 | V | Tamb=-40℃; VO=1, 9 V; VDD=10 V | 9 | ||
| HIGH-level input voltage | VIH | 11 | V | Tamb=-40℃; VO=1.5, 13.5 V; VDD=15 V | 9 |
CAD (KiCad official)
- Symbol:
AiP74HC4094SA16.TB - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
aip74hc4094sa16-tb-etched.step/aip74hc4094sa16-tb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc4094sa16-tb.step/aip74hc4094sa16-tb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (17 pp, sha256
a102a16b792933fe, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AiP74HC4094SA16.TB
**Wuxi I core Elec** · Inverters · SOP-16
AiP74HC4094SA16.TB from Wuxi I core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input: data in each shift register stage is transferred to the storage register when STR is HIGH. |
| 2 | D | input | Serial data input, shifted into the 8-stage register on positive-going clock transitions. |
| 3 | CP | input | Clock input: data is shifted on positive-going clock transitions. |
| 4 | QP0 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 5 | QP1 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 6 | QP2 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 7 | QP3 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 8 | VSS | power_in | Ground (0V) reference; the recommended VDD range of 3V to 15V is referenced to VSS. |
| 9 | QS1 | output | Serial output for cascading that carries serial data on positive-going clock edges, allowing high-speed operation with a fast clock rise time. |
| 10 | QS2 | output | Serial output for cascading that carries the same serial data as QS1 on the next negative-going clock edge, used when the clock has a slow rise time. |
| 11 | QP7 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 12 | QP6 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 13 | QP5 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 14 | QP4 | tri_state | Buffered 3-state parallel output that may be connected directly to common bus lines; data appears here whenever OE is HIGH. |
| 15 | OE | input | Output enable input: the parallel outputs are active when OE is HIGH and go to high-impedance OFF-state when OE is LOW. |
| 16 | VDD | power_in | Supply voltage; recommended range is 3V to 15V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VDD | -0.5 | | 18 | V | | 6 |
| DC input current | IIK | -10 | | 10 | mA | any one input | 6 |
| input voltage | VI | -0.5 | | | V | all inputs; max printed as VDD+0.5 V | 6 |
| storage temperature | Tstg | -65 | | 150 | ℃ | | 6 |
| total power dissipation | Ptot | | | 500 | mW | | 6 |
| device dissipation per output transistor | P | | | 100 | mW | per output transistor | 6 |
| supply voltage | VDD | 3 | | 15 | V | | 7 |
| ambient temperature | Tamb | -40 | | 105 | ℃ | in free air | 7 |
| data setup time | tsu | 125 | | | ns | VDD=5V | 7 |
| data setup time | tsu | 55 | | | ns | VDD=10V | 7 |
| data setup time | tsu | 35 | | | ns | VDD=15V | 7 |
| clock pulse width | tw | 200 | | | ns | VDD=5V | 7 |
| clock pulse width | tw | 100 | | | ns | VDD=10V | 7 |
| clock pulse width | tw | 83 | | | ns | VDD=15V | 7 |
| clock input frequency | fmax | | | 1.25 | MHz | VDD=5V; printed minimum is dc | 7 |
| clock input frequency | fmax | | | 2.5 | MHz | VDD=10V | 7 |
| clock input frequency | fmax | | | 3 | MHz | VDD=15V | 7 |
| supply current | IDD | | | 5 | uA | Tamb=-40℃; VIN=0, 5 V; VDD=5 V | 9 |
| supply current | IDD | | | 150 | uA | Tamb=+105℃; VIN=0, 5 V; VDD=5 V | 9 |
| supply current | IDD | | | 10 | uA | Tamb=-40℃; VIN=0, 10 V; VDD=10 V | 9 |
| supply current | IDD | | | 300 | uA | Tamb=+105℃; VIN=0, 10 V; VDD=10 V | 9 |
| supply current | IDD | | | 20 | uA | Tamb=-40℃; VIN=0, 15 V; VDD=15 V | 9 |
| supply current | IDD | | | 600 | uA | Tamb=+105℃; VIN=0, 15 V; VDD=15 V | 9 |
| LOW-level output current | IOL | 0.61 | | | mA | Tamb=-40℃; VO=0.4 V; VIN=0, 5 V; VDD=5 V | 9 |
| LOW-level output current | IOL | 0.36 | | | mA | Tamb=+105℃; VO=0.4 V; VIN=0, 5 V; VDD=5 V | 9 |
| LOW-level output current | IOL | 1.5 | | | mA | Tamb=-40℃; VO=0.5 V; VIN=0, 10 V; VDD=10 V | 9 |
| LOW-level output current | IOL | 0.9 | | | mA | Tamb=+105℃; VO=0.5 V; VIN=0, 10 V; VDD=10 V | 9 |
| LOW-level output current | IOL | 4 | | | mA | Tamb=-40℃; VO=1.5 V; VIN=0, 15 V; VDD=15 V | 9 |
| LOW-level output current | IOL | 2.4 | | | mA | Tamb=+105℃; VO=1.5 V; VIN=0, 15 V; VDD=15 V | 9 |
| HIGH-level output current | IOH | -0.61 | | | mA | Tamb=-40℃; VO=4.6 V; VIN=0, 5 V; VDD=5 V | 9 |
| HIGH-level output current | IOH | -0.36 | | | mA | Tamb=+105℃; VO=4.6 V; VIN=0, 5 V; VDD=5 V | 9 |
| HIGH-level output current | IOH | -1.8 | | | mA | Tamb=-40℃; VO=2.5 V; VIN=0, 5 V; VDD=5 V | 9 |
| HIGH-level output current | IOH | -1.15 | | | mA | Tamb=+105℃; VO=2.5 V; VIN=0, 5 V; VDD=5 V | 9 |
| HIGH-level output current | IOH | -1.5 | | | mA | Tamb=-40℃; VO=9.5 V; VIN=0, 10 V; VDD=10 V | 9 |
| HIGH-level output current | IOH | -0.9 | | | mA | Tamb=+105℃; VO=9.5 V; VIN=0, 10 V; VDD=10 V | 9 |
| HIGH-level output current | IOH | -4 | | | mA | Tamb=-40℃; VO=13.5 V; VIN=0, 15 V; VDD=15 V | 9 |
| HIGH-level output current | IOH | -2.4 | | | mA | Tamb=+105℃; VO=13.5 V; VIN=0, 15 V; VDD=15 V | 9 |
| LOW-level output voltage | VOL | | | 0.05 | V | Tamb=-40℃; VIN=0, 5 V; VDD=5 V | 9 |
| HIGH-level output voltage | VOH | 4.95 | | | V | Tamb=-40℃; VIN=0, 5 V; VDD=5 V | 9 |
| HIGH-level output voltage | VOH | 9.95 | | | V | Tamb=-40℃; VIN=0, 10 V; VDD=10 V | 9 |
| HIGH-level output voltage | VOH | 14.95 | | | V | Tamb=-40℃; VIN=0, 15 V; VDD=15 V | 9 |
| LOW-level input voltage | VIL | | | 1.5 | V | Tamb=-40℃; VO=0.5, 4.5 V; VDD=5 V | 9 |
| LOW-level input voltage | VIL | | | 3 | V | Tamb=-40℃; VO=1, 9 V; VDD=10 V | 9 |
| LOW-level input voltage | VIL | | | 4 | V | Tamb=-40℃; VO=1.5, 13.5 V; VDD=15 V | 9 |
| HIGH-level input voltage | VIH | 3.5 | | | V | Tamb=-40℃; VO=0.5, 4.5 V; VDD=5 V | 9 |
| HIGH-level input voltage | VIH | 7 | | | V | Tamb=-40℃; VO=1, 9 V; VDD=10 V | 9 |
| HIGH-level input voltage | VIH | 11 | | | V | Tamb=-40℃; VO=1.5, 13.5 V; VDD=15 V | 9 |
## CAD (KiCad official)
- Symbol: `AiP74HC4094SA16.TB`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `aip74hc4094sa16-tb-etched.step` / `aip74hc4094sa16-tb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `aip74hc4094sa16-tb.step` / `aip74hc4094sa16-tb.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Wuxi I core Elec datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590236407911919616) (17 pp, sha256 `a102a16b792933fe`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/aip74hc4094sa16-tb-datasheet.pdf)