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AIP74HC4052SA16.TR

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Wuxi I core Elec Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AIP74HC4052SA16.TR

Wuxi I core Elec · Analog Switches, Multiplexers · SOP-16

AIP74HC4052SA16.TR from Wuxi I core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 2Y0 passive Independent analog input/output nY0 of switch 2; it connects to common terminal 2Z when E̅ is LOW and S1=L, S0=L, and the switch voltage must stay between VEE and VCC.
2 2Y2 passive Independent analog input/output nY2 of switch 2; it connects to common terminal 2Z when E̅ is LOW and S1=H, S0=L, and the switch voltage must stay between VEE and VCC.
3 2Z passive Common analog input/output of switch 2; it connects to the selected 2Yn channel when E̅ is LOW, with switch current limited to ±25 mA absolute maximum.
4 2Y3 passive Independent analog input/output nY3 of switch 2; it connects to common terminal 2Z when E̅ is LOW and S1=H, S0=H, and the switch voltage must stay between VEE and VCC.
5 2Y1 passive Independent analog input/output nY1 of switch 2; it connects to common terminal 2Z when E̅ is LOW and S1=L, S0=H, and the switch voltage must stay between VEE and VCC.
6 E input Active-LOW enable input; when HIGH all switches are turned off, and the input clamping current is limited to ±20 mA absolute maximum.
7 VEE power_in Negative supply voltage for the analog switches; recommended VCC - VEE is 3.0 V to 9.0 V, and supply current IEE is limited to ±20 mA absolute maximum.
8 GND power_in Ground supply voltage and 0 V reference for the logic inputs; ground current IGND is limited to -50 mA absolute maximum.
9 S1 input Digital select input (most significant bit) choosing which nYn channel connects to nZ; for the AiP74HC4052 it uses CMOS input levels with input voltage range 0 V to VCC.
10 S0 input Digital select input (least significant bit) choosing which nYn channel connects to nZ; for the AiP74HC4052 it uses CMOS input levels with input voltage range 0 V to VCC.
11 1Y3 passive Independent analog input/output nY3 of switch 1; it connects to common terminal 1Z when E̅ is LOW and S1=H, S0=H, and the switch voltage must stay between VEE and VCC.
12 1Y0 passive Independent analog input/output nY0 of switch 1; it connects to common terminal 1Z when E̅ is LOW and S1=L, S0=L, and the switch voltage must stay between VEE and VCC.
13 1Z passive Common analog input/output of switch 1; it connects to the selected 1Yn channel when E̅ is LOW, with switch current limited to ±25 mA absolute maximum.
14 1Y1 passive Independent analog input/output nY1 of switch 1; it connects to common terminal 1Z when E̅ is LOW and S1=L, S0=H, and the switch voltage must stay between VEE and VCC.
15 1Y2 passive Independent analog input/output nY2 of switch 1; it connects to common terminal 1Z when E̅ is LOW and S1=H, S0=L, and the switch voltage must stay between VEE and VCC.
16 VCC power_in Positive supply voltage; recommended VCC - GND is 3.0 V to 9.0 V for the AiP74HC4052 and the absolute maximum supply voltage is +11 V.

Key specifications

Parameter Value
Manufacturer Wuxi I core Elec
Package SOP-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: AIP74HC4052SA16.TR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: aip74hc4052sa16-tr-etched.step / aip74hc4052sa16-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc4052sa16-tr.step / aip74hc4052sa16-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I core Elec datasheet (28 pp, sha256 4b986711a66b21f0, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF