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AiP74HC373SA20.TB

Wuxi I-core Elec · Latches · SOP-20-300mil

AiP74HC373SA20.TB from Wuxi I-core Elec, in a SOP-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input 3-state output enable input (active LOW); a HIGH puts the outputs in high-impedance OFF-state without affecting the latches.
2 Q0 tri_state 3-state latch output.
3 D0 input Data input.
4 D1 input Data input.
5 Q1 tri_state 3-state latch output.
6 Q2 tri_state 3-state latch output.
7 D2 input Data input.
8 D3 input Data input.
9 Q3 tri_state 3-state latch output.
10 GND power_in Ground (0V).
11 LE input Latch enable input (active HIGH); latches are transparent when HIGH and store data when LOW.
12 Q4 tri_state 3-state latch output.
13 D4 input Data input.
14 D5 input Data input.
15 Q5 tri_state 3-state latch output.
16 Q6 tri_state 3-state latch output.
17 D6 input Data input.
18 D7 input Data input.
19 Q7 tri_state 3-state latch output.
20 VCC power_in Supply voltage; 2.0V to 6.0V recommended for AiP74HC373, absolute maximum 7.0V.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package SOP-20-300mil
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 8
Input clamping current IIK 20 mA VI < -0.5V or VI > VCC+0.5V (±20) 8
Output clamping current IOK 20 mA VO < -0.5V or VO > VCC+0.5V (±20) 8
Output current IO 35 mA VO= -0.5V to (VCC+0.5V) (±35) 8
Supply current ICC 70 mA 8
Ground current IGND -70 mA 8
Storage temperature Tstg -65 150 ℃ 8
Total power dissipation Ptot 500 mW SOP20: above 70℃ derates linearly with 8mW/K 8
Soldering temperature TL 250 ℃ 10s, SOP 8
Supply voltage VCC 2 5 6 V AiP74HC373 8
Input voltage VI 0 V max printed as VCC 8
Output voltage VO 0 V max printed as VCC 8
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 8
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 8
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 8
Ambient temperature Tamb -40 105 ℃ 8
HIGH-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40℃ to +105℃ 11
HIGH-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40℃ to +105℃ 11
HIGH-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40℃ to +105℃ 11
LOW-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40℃ to +105℃ 11
LOW-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40℃ to +105℃ 11
LOW-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO=-20uA; VCC=2.0V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO=-20uA; VCC=4.5V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO=-20uA; VCC=6.0V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO=-6.0mA; VCC=4.5V; Tamb=-40℃ to +105℃ 11
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO=-7.8mA; VCC=6.0V; Tamb=-40℃ to +105℃ 11
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO=20uA; VCC=2.0V; Tamb=-40℃ to +105℃ 11
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO=6.0mA; VCC=4.5V; Tamb=-40℃ to +105℃ 11
Input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V; Tamb=-40℃ to +105℃ 11
OFF-state output current IOZ -10 10 uA VI=VIH or VIL; VCC=6.0V; VO=VCC or GND; Tamb=-40℃ to +105℃ 11
Supply current ICC 160 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=-40℃ to +105℃ 11
Input leakage current II -0.1 0.1 uA VI=VCC or GND; VCC=6.0V; Tamb=25℃ 9
OFF-state output current IOZ -0.5 0.5 uA VI=VIH or VIL; VCC=6.0V; VO=VCC or GND; Tamb=25℃ 9
Supply current ICC 8 uA VI=VCC or GND; IO=0A; VCC=6.0V; Tamb=25℃ 9
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO=-6.0mA; VCC=4.5V; Tamb=25℃ 9
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; IO=6.0mA; VCC=4.5V; Tamb=25℃ 9
Propagation delay Dn to Qn tpd 225 ns VCC=2.0V; see Figure 7; Tamb=-40℃ to +105℃; CL=50pF 14
Propagation delay Dn to Qn tpd 45 ns VCC=4.5V; see Figure 7; Tamb=-40℃ to +105℃; CL=50pF 14
Propagation delay Dn to Qn tpd 38 ns VCC=6.0V; see Figure 7; Tamb=-40℃ to +105℃; CL=50pF 14
Propagation delay LE to Qn tpd 265 ns VCC=2.0V; see Figure 8; Tamb=-40℃ to +105℃; CL=50pF 14
Propagation delay LE to Qn tpd 53 ns VCC=4.5V; see Figure 8; Tamb=-40℃ to +105℃; CL=50pF 14
Propagation delay LE to Qn tpd 45 ns VCC=6.0V; see Figure 8; Tamb=-40℃ to +105℃; CL=50pF 14
OE to Qn enable time ten 45 ns VCC=4.5V; see Figure 9; Tamb=-40℃ to +105℃; CL=50pF 14
OE to Qn disable time tdis 45 ns VCC=4.5V; see Figure 9; Tamb=-40℃ to +105℃; CL=50pF 14
Transition time tt 18 ns Qn; VCC=4.5V; see Figure 7, 8; Tamb=-40℃ to +105℃; CL=50pF 14
Pulse width LE HIGH tW 24 ns VCC=4.5V; see Figure 8; Tamb=-40℃ to +105℃ 14
Set-up time Dn to LE tsu 15 ns VCC=4.5V; see Figure 10; Tamb=-40℃ to +105℃ 14
Hold time Dn to LE th 5 ns VCC=4.5V; see Figure 10; Tamb=-40℃ to +105℃ 15
Propagation delay Dn to Qn tpd 15 30 ns VCC=4.5V; see Figure 7; Tamb=25℃; CL=50pF 12
Input capacitance CI 3.5 pF Tamb=25℃ 9
Power dissipation capacitance CPD 45 pF per latch; VI=GND to VCC; Tamb=25℃ 12

CAD (KiCad official)

  • Symbol: AiP74HC373SA20.TB
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20-300mil, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: aip74hc373sa20-tb-etched.step / aip74hc373sa20-tb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc373sa20-tb.step / aip74hc373sa20-tb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (21 pp, sha256 e69ef16e87b2e3ed, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF