component
AiP74HC165SA16.TR
Public Made by Adomby adom
Wuxi I core Elec Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+507−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/aip74hc165sa16-tr-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+505@@ -0,0 +1,505 @@+{+ "schema": "adom.pads/1",+ "slug": "aip74hc165sa16-tr",+ "footprint": "SOIC-16_3.9x9.9mm_P1.27mm",+ "generated_from": {+ "footprint": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -4.445+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c"+ },+ "pad_count": 16,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "PL",+ "type": "input",+ "description": "Asynchronous parallel load input, active low. When PL=L, data on D0-D7 is loaded into the shift register regardless of CP.",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "CP",+ "type": "input",+ "description": "Clock input, low-to-high edge triggered. Shifts serial data through the register when CE is low and PL is high.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "D4",+ "type": "input",+ "description": "Parallel data input bit 4 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "D5",+ "type": "input",+ "description": "Parallel data input bit 5 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "D6",+ "type": "input",+ "description": "Parallel data input bit 6 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "D7",+ "type": "input",+ "description": "Parallel data input bit 7 (Dn). Last stage that appears at Q7 after a parallel load.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "/Q7",+ "type": "output",+ "description": "Complementary serial output of the last (Q7) stage. Inverse of the Q7 pin.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "9",+ "name": "Q7",+ "type": "output",+ "description": "Serial output from the last (Q7) stage of the shift register.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "10",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "10",+ "name": "DS",+ "type": "input",+ "description": "Serial data input. Shifted into stage Q0 on each CP rising edge while CE is low and PL is high.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "11",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "11",+ "name": "D0",+ "type": "input",+ "description": "Parallel data input bit 0 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "12",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "12",+ "name": "D1",+ "type": "input",+ "description": "Parallel data input bit 1 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "13",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "13",+ "name": "D2",+ "type": "input",+ "description": "Parallel data input bit 2 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "14",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "14",+ "name": "D3",+ "type": "input",+ "description": "Parallel data input bit 3 (Dn). Loaded into the corresponding shift-register stage when PL is low.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "15",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "15",+ "name": "CE",+ "type": "input",+ "description": "Clock enable input, active low. When CE is low the clock is enabled; a high on CE inhibits (gates off) the CP input.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "16",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. AiP74HC165: 2.0-6.0 V (5.0 V typ). AiP74HCT165: 4.5-5.5 V (5.0 V typ). Absolute max +7 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}