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AiP74HC123SA16.TR

Wuxi I core Elec · Flip Flops · SOP-16

AiP74HC123SA16.TR from Wuxi I core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Falling-edge trigger input 1 (the datasheet calls it the falling-edge triggered input 1, active on a high-to-low transition).
2 1B input Rising-edge trigger input 1 (the datasheet calls it the rising-edge triggered input 1, active on a low-to-high transition).
3 1RD input Direct reset input 1 (active low) and rising-edge trigger input 1; a low level on this pin terminates the output pulse directly.
4 ~{1Q} output Low-level (inverted) output 1, the complement of 1Q.
5 2Q output High-level (non-inverted) output 2.
6 2CEXT passive External capacitor connection 2 for the timing network; the datasheet notes that tying pin 6 to GND (pin 8) minimizes noise.
7 2REXT/CEXT passive External resistor and capacitor connection 2; at VCC=5.0V the external timing resistor REXT is specified from 2 kΩ to 1000 kΩ.
8 GND power_in Ground (0 V) reference for the device.
9 2A input Falling-edge trigger input 2 (the datasheet calls it the falling-edge triggered input 2, active on a high-to-low transition).
10 2B input Rising-edge trigger input 2 (the datasheet calls it the rising-edge triggered input 2, active on a low-to-high transition).
11 2RD input Direct reset input 2 (active low) and rising-edge trigger input 2; a low level on this pin terminates the output pulse directly.
12 ~{2Q} output Low-level (inverted) output 2, the complement of 2Q.
13 1Q output High-level (non-inverted) output 1.
14 1CEXT passive External capacitor connection 1 for the timing network; the datasheet notes that tying pin 14 to GND (pin 8) minimizes noise.
15 1REXT/CEXT passive External resistor and capacitor connection 1; at VCC=5.0V the external timing resistor REXT is specified from 2 kΩ to 1000 kΩ.
16 VCC power_in Supply voltage; recommended range is 2.0 V to 6.0 V for the AiP74HC123 (absolute maximum 7.0 V).

Key specifications

Parameter Value
Manufacturer Wuxi I core Elec
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 8
Input clamp current IIK -20 20 mA VI<-0.5V or VI>VCC+0.5V 8
Output clamp current IOK -20 20 mA VO<-0.5V or VO>VCC+0.5V 8
Output current IO -25 25 mA nREXT/CEXT excluded; VO=-0.5V to (VCC+0.5V) 8
Supply current ICC 50 mA 8
Ground current IGND -50 mA 8
Storage temperature Tstg -65 150 ℃ 8
Total power dissipation Ptot 500 mW 8
Soldering temperature, SOP TL 250 ℃ 10 s; SOP package 8
Supply voltage (recommended) VCC 2 5 6 V 8
Input voltage VI 0 V 8
Output voltage VO 0 V 8
Input rise and fall rate nRD input Δt/ΔV 625 ns/V nRD input; VCC=2.0V 8
Input rise and fall rate nRD input Δt/ΔV 1.67 139 ns/V nRD input; VCC=4.5V 8
Input rise and fall rate nRD input Δt/ΔV 83 ns/V nRD input; VCC=6.0V 8
Operating ambient temperature Tamb -40 105 ℃ 8
High-level input voltage VIH 1.5 V VCC=2.0V; Tamb=-40℃~+105℃ 11
High-level input voltage VIH 3.15 V VCC=4.5V; Tamb=-40℃~+105℃ 11
High-level input voltage VIH 4.2 V VCC=6.0V; Tamb=-40℃~+105℃ 11
Low-level input voltage VIL 0.5 V VCC=2.0V; Tamb=-40℃~+105℃ 11
Low-level input voltage VIL 1.35 V VCC=4.5V; Tamb=-40℃~+105℃ 11
Low-level input voltage VIL 1.8 V VCC=6.0V; Tamb=-40℃~+105℃ 11
High-level output voltage VOH 1.9 V VI=VIH或VIL; IO=-20uA; VCC=2.0V; Tamb=-40℃~+105℃ 11
High-level output voltage VOH 4.4 V VI=VIH或VIL; IO=-20uA; VCC=4.5V; Tamb=-40℃~+105℃ 11
High-level output voltage VOH 5.9 V VI=VIH或VIL; IO=-20uA; VCC=6.0V; Tamb=-40℃~+105℃ 11
High-level output voltage VOH 3.7 V VI=VIH或VIL; IO=-4mA; VCC=4.5V; Tamb=-40℃~+105℃ 11
High-level output voltage VOH 5.2 V VI=VIH或VIL; IO=-5.2mA; VCC=6.0V; Tamb=-40℃~+105℃ 11
Low-level output voltage VOL 0.1 V VI=VIH或VIL; IO=20uA; VCC=2.0V; Tamb=-40℃~+105℃ 11
Low-level output voltage VOL 0.4 V VI=VIH或VIL; IO=4mA; VCC=4.5V; Tamb=-40℃~+105℃ 11
Input leakage current II -1 1 uA VI=VCC或GND; VCC=6.0V; Tamb=-40℃~+105℃ 11
Static current ICC 160 uA VI=VCC或GND; IO=0A; VCC=6.0V; Tamb=-40℃~+105℃ 11
Transition time, max tt 22 ns VCC=4.5V; CL=50pF; 见图6; Tamb=-40℃~+105℃ 16
Pulse width nA low, min tW 30 ns VCC=4.5V; nA=低电平; 见图7; Tamb=-40℃~+105℃ 16
Pulse width nB high, min tW 30 ns VCC=4.5V; nB=高电平; 见图7; Tamb=-40℃~+105℃ 16
Pulse width nRD low, min tW 30 ns VCC=4.5V; nRD=低电平; 见图8; Tamb=-40℃~+105℃ 16
External timing resistor REXT REXT 10 1000 kΩ VCC=2.0V; 见图7; Tamb=25℃ 12
External timing resistor REXT REXT 2 1000 kΩ VCC=5.0V; 见图7; Tamb=25℃ 12
Propagation delay nRD/nA/nB to nQ or nQ-bar, max tpd 83 255 ns VCC=2.0V; CL=50pF; CEXT=0pF; REXT=5kΩ; 见图6; Tamb=25℃ 12
Propagation delay nRD/nA/nB to nQ or nQ-bar, max tpd 30 51 ns VCC=4.5V; CL=50pF; CEXT=0pF; REXT=5kΩ; 见图6; Tamb=25℃ 12
Propagation delay nRD/nA/nB to nQ or nQ-bar, max tpd 24 43 ns VCC=6.0V; CL=50pF; CEXT=0pF; REXT=5kΩ; 见图6; Tamb=25℃ 12
Transition time, max tt 7 15 ns VCC=4.5V; CL=50pF; 见图6; Tamb=25℃ 12
Static current ICC 8 uA VI=VCC或GND; IO=0A; VCC=6.0V; Tamb=25℃ 9
Input capacitance CI 3.5 pF Tamb=25℃ 9

CAD (KiCad official)

  • Symbol: AiP74HC123SA16.TR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: aip74hc123sa16-tr-etched.step / aip74hc123sa16-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc123sa16-tr.step / aip74hc123sa16-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I core Elec datasheet (25 pp, sha256 0b97f4a95f3b0e32, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF