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AIP74HC123

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Wuxi I-core Elec Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic icsaip74hc123factory-2.0.0extractor-text

Verified AIP74HC123

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AIP74HC123 · SOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 26-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-16_3.9x9.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-59xnpvmd/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ aip74hc123.kicad_sym✓ aip74hc123.kicad_mod✓ aip74hc123.step
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Symbol & Footprint

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Contents

README

markdown

AIP74HC123

Wuxi I-core Elec · Flip Flops · SOP-16

AIP74HC123 from Wuxi I-core Elec, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Negative-edge triggered input 1 (active-LOW going edge triggers the monostable; the basic output pulse is set by external REXT and CEXT).
2 1B input Positive-edge triggered input 1 (active-HIGH going edge triggers the monostable; the basic output pulse is set by external REXT and CEXT).
3 1RD input Direct reset LOW and positive-edge triggered input 1; a LOW level terminates the output pulse and inhibits triggering.
4 1Q output Active LOW output 1; the output pulse is HIGH on nQ and LOW on this pin for the monostable period.
5 2Q output Active HIGH output 2; goes HIGH for the programmed output pulse width after a valid trigger.
6 2CEXT passive External capacitor connection 2; for minimum noise generation it is recommended to ground this pin externally to pin 8 (GND).
7 2REXT/CEXT passive External resistor and capacitor connection 2 used to set the output pulse width of monostable 2.
8 GND power_in Ground (0V) reference for all voltages.
9 2A input Negative-edge triggered input 2 (active-LOW going edge triggers the monostable).
10 2B input Positive-edge triggered input 2 (active-HIGH going edge triggers the monostable).
11 2RD input Direct reset LOW and positive-edge triggered input 2; a LOW level terminates the output pulse and inhibits triggering.
12 2Q output Active LOW output 2; the complementary output of monostable 2 (nQ-bar).
13 1Q output Active HIGH output 1; goes HIGH for the programmed output pulse width after a valid trigger.
14 1CEXT passive External capacitor connection 1; for minimum noise generation it is recommended to ground this pin externally to pin 8 (GND).
15 1REXT/CEXT passive External resistor and capacitor connection 1 used to set the output pulse width of monostable 1.
16 VCC power_in Supply voltage; the AiP74HC123 operates from 2.0V to 6.0V and the AiP74HCT123 from 4.5V to 5.5V.

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package SOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 2 5 6 V 8
input voltage VI 0 V 8
output voltage VO 0 V 8
input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V; nRD input 8
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V; nRD input 8
input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V; nRD input 8
ambient temperature Tamb -40 105 ℃ 8
supply voltage VCC -0.5 7 V 8
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 8
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 8
output current IO -25 25 mA except for pins nREXT/CEXT; VO= -0.5V to (VCC+0.5V) 8
supply current ICC 50 mA 8
ground current IGND -50 mA 8
storage temperature Tstg -65 150 ℃ 8
total power dissipation Ptot 500 mW 8
soldering temperature (SOP) TL 250 ℃ 10s; SOP 8
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V 9
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V 9
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V 9
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V 9
LOW-level input voltage VIL 2.1 1.35 V VCC=4.5V 9
LOW-level input voltage VIL 2.8 1.8 V VCC=6.0V 9
HIGH-level output voltage VOH 1.9 2 V VI=VIH or VIL; IO=-20uA; VCC=2.0V 9
HIGH-level output voltage VOH 4.4 4.5 V VI=VIH or VIL; IO=-20uA; VCC=4.5V 9
HIGH-level output voltage VOH 5.9 6 V VI=VIH or VIL; IO=-20uA; VCC=6.0V 9
HIGH-level output voltage VOH 3.98 4.32 V VI=VIH or VIL; IO=-4mA; VCC=4.5V 9
HIGH-level output voltage VOH 5.48 5.81 V VI=VIH or VIL; IO=-5.2mA; VCC=6.0V 9
LOW-level output voltage VOL 0 0.1 V VI=VIH or VIL; IO=20uA; VCC=2.0V 9
LOW-level output voltage VOL 0.15 0.26 V VI=VIH or VIL; IO=4mA; VCC=4.5V 9
LOW-level output voltage VOL 0.16 0.26 V VI=VIH or VIL; IO=5.2mA; VCC=6.0V 9
input leakage current II -0.1 0.1 uA VI=VCC or GND; VCC=6.0V 9
supply current ICC 8 uA VI=VCC or GND; IO=0A; VCC=6.0V 9
HIGH-level input voltage VIH 1.5 V VCC=2.0V 11
HIGH-level input voltage VIH 3.15 V VCC=4.5V 11
HIGH-level input voltage VIH 4.2 V VCC=6.0V 11
LOW-level input voltage VIL 0.5 V VCC=2.0V 11
LOW-level input voltage VIL 1.35 V VCC=4.5V 11
LOW-level input voltage VIL 1.8 V VCC=6.0V 11
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO=-20uA; VCC=2.0V 11
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO=-20uA; VCC=4.5V 11
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO=-20uA; VCC=6.0V 11
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO=-4mA; VCC=4.5V 11
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO=-5.2mA; VCC=6.0V 11
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO=20uA; VCC=2.0V 11
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO=4mA; VCC=4.5V 11
input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V 11
supply current ICC 160 uA VI=VCC or GND; IO=0A; VCC=6.0V 11
propagation delay tpd tpd 385 ns nRD, nA, nB to nQ or nQ; CEXT=0pF; REXT=5kΩ; VCC=2.0V; Tamb=-40℃ to +105℃ 15
propagation delay tpd tpd 77 ns nRD, nA, nB to nQ or nQ; CEXT=0pF; REXT=5kΩ; VCC=4.5V; Tamb=-40℃ to +105℃ 15
propagation delay tpd tpd 65 ns nRD, nA, nB to nQ or nQ; CEXT=0pF; REXT=5kΩ; VCC=6.0V; Tamb=-40℃ to +105℃ 15
nRD (reset) to nQ or nQ propagation delay tpd 325 ns CEXT=0pF; REXT=5kΩ; VCC=2.0V; Tamb=-40℃ to +105℃ 15
nRD (reset) to nQ or nQ propagation delay tpd 65 ns CEXT=0pF; REXT=5kΩ; VCC=4.5V; Tamb=-40℃ to +105℃ 15
nRD (reset) to nQ or nQ propagation delay tpd 55 ns CEXT=0pF; REXT=5kΩ; VCC=6.0V; Tamb=-40℃ to +105℃ 15
transition time tt 22 ns VCC=4.5V; see Figure 6; Tamb=-40℃ to +105℃ 15

CAD (KiCad official)

  • Symbol: AIP74HC123
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: aip74hc123-etched.step / aip74hc123-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc123.step / aip74hc123.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (26 pp, sha256 0465ec144b8d40e4, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF