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AiP74HC02SA14.TR

Public Made by Adom

by adom

Wuxi I core Elec Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs aip74hc02sa14-tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers aip74hc02sa14-tr: viewers · Ray 2mo ago
aip74hc02sa14-tr-etched.fit.json aip74hc02sa14-tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
aip74hc02sa14-tr-etched.glb aip74hc02sa14-tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
aip74hc02sa14-tr-etched.step aip74hc02sa14-tr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
aip74hc02sa14-tr.glb Publish 0.1.0 · Ray 2mo ago
aip74hc02sa14-tr.kicad_mod Publish 0.1.0 · Ray 2mo ago
aip74hc02sa14-tr.kicad_sym Publish 0.1.0 · Ray 2mo ago
aip74hc02sa14-tr.lbr aip74hc02sa14-tr: factory component page (tier=lcsc) · Ray 2mo ago
aip74hc02sa14-tr.step Publish 0.1.0 · Ray 2mo ago
package.json aip74hc02sa14-tr: manufacturer 'Wuxi I core Elec' (was 'Wuxi I core Elec AiP74HC02SA14 TR': the MPN had been folded in) · Ray 1mo ago
page.json aip74hc02sa14-tr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md aip74hc02sa14-tr: manufacturer 'Wuxi I core Elec' (was 'Wuxi I core Elec AiP74HC02SA14 TR': the MPN had been folded in) · Ray 1mo ago

AiP74HC02SA14.TR

Wuxi I core Elec · Gates · SOP-14

AiP74HC02SA14.TR from Wuxi I core Elec, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Gate 1 data output. NOR output of inputs 1A and 1B. HIGH only when both 1A and 1B are LOW.
2 1A input Gate 1 data input A. CMOS logic input with clamp diodes.
3 1B input Gate 1 data input B. CMOS logic input with clamp diodes.
4 2Y output Gate 2 data output. NOR output of inputs 2A and 2B. HIGH only when both 2A and 2B are LOW.
5 2A input Gate 2 data input A. CMOS logic input with clamp diodes.
6 2B input Gate 2 data input B. CMOS logic input with clamp diodes.
7 GND power_in Ground (0V) reference. All voltages referenced to this pin.
8 3A input Gate 3 data input A. CMOS logic input with clamp diodes.
9 3B input Gate 3 data input B. CMOS logic input with clamp diodes.
10 3Y output Gate 3 data output. NOR output of inputs 3A and 3B. HIGH only when both 3A and 3B are LOW.
11 4A input Gate 4 data input A. CMOS logic input with clamp diodes.
12 4B input Gate 4 data input B. CMOS logic input with clamp diodes.
13 4Y output Gate 4 data output. NOR output of inputs 4A and 4B. HIGH only when both 4A and 4B are LOW.
14 VCC power_in Positive supply voltage. Operating range 2.0V to 6.0V (recommended); absolute max 7V. Bypass with 100nF to GND close to the pin.

Key specifications

Parameter Value
Manufacturer Wuxi I core Elec
Package SOP-14
Category Logic
Pins 14

Ordering variants

  • AiP74HC02SA14.TR
  • AiP74HC02SA14.TRSA14.TB
  • AiP74HC02SA14.TRDA14.TB
  • AiP74HC02SA14.TRTA14.TR
  • AiP74HC02SA14.TRTA14.TB

CAD (KiCad official)

  • Symbol: AiP74HC02SA14.TR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: aip74hc02sa14-tr-etched.step / aip74hc02sa14-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc02sa14-tr.step / aip74hc02sa14-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I core Elec datasheet (17 pp, sha256 b8c4af095b3d023a, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF